Datasheet

Ê80 : "+r" (delay_cyc)
Ê81 );
Ê82 }
Ê83 }
Ê84
Ê85 // Set aux mux first, and then glitchless mux if this clock has one
Ê86 hw_write_masked(&clock->ctrl,
Ê87 (auxsrc << CLOCKS_CLK_SYS_CTRL_AUXSRC_LSB),
Ê88 CLOCKS_CLK_SYS_CTRL_AUXSRC_BITS
Ê89 );
Ê90
Ê91 if (has_glitchless_mux(clk_index)) {
Ê92 hw_write_masked(&clock->ctrl,
Ê93 src << CLOCKS_CLK_REF_CTRL_SRC_LSB,
Ê94 CLOCKS_CLK_REF_CTRL_SRC_BITS
Ê95 );
Ê96 while (!(clock->selected & (1u << src)))
Ê97 tight_loop_contents();
Ê98 }
Ê99
100 hw_set_bits(&clock->ctrl, CLOCKS_CLK_GPOUT0_CTRL_ENABLE_BITS);
101
102 // Now that the source is configured, we can trust that the user-supplied
103 // divisor is a safe value.
104 clock->div = div;
105
106 // Store the configured frequency
107 configured_freq[clk_index] = freq;
108
109 return 0;
110 }
It is called in clocks_init for each clock. The following example shows the clk_sys configuration:
Pico SDK: https://github.com/raspberrypi/pico-sdk/tree/pre_release/src/rp2_common/hardware_clocks/clocks.c Lines 161 - 166
161 // CLK SYS = PLL SYS (125MHz) / 1 = 125MHz
162 clock_configure(clk_sys,
163 CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLKSRC_CLK_SYS_AUX,
164 CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS,
165 125 * MHZ,
166 125 * MHZ);
Once a clock is configured, clock_get_hz can be called to get the output frequency in Hz.
Pico SDK: https://github.com/raspberrypi/pico-sdk/tree/pre_release/src/rp2_common/hardware_clocks/clocks.c Lines 200 - 202
200 uint32_t clock_get_hz(enum clock_index clk_index) {
201 return configured_freq[clk_index];
202 }
RP2040 Datasheet
2.14. Clocks 170