Datasheet

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USB 1.1 Host/Device
1.3. The Chip
RP2040 has a dual M0+ processor cores, DMA, internal memory and peripheral blocks connected via AHB/APB bus fabric.
Figure 2. A system
overview of the
RP2040 chip
Code may be executed directly from external memory through a dedicated SPI, DSPI or QSPI interface. A small cache
improves performance for typical applications.
Debug is available via the SWD interface.
Internal SRAM is arranged in banks which can contain code or data and is accessed via dedicated AHB bus fabric
connections, allowing bus masters to access separate bus slaves without being stalled.
DMA bus masters are available to offload repetitive data transfer tasks from the processors.
GPIO pins can be driven directly, or from a variety of dedicated logic functions.
Dedicated hardware for fixed functions such as SPI, I2C, UART.
Flexible configurable PIO controllers can be used to provide a wide variety of IO functions.
A USB controller with embedded PHY can be used to provide FS/LS Host or Device connectivity under software control.
Four ADC inputs which are shared with GPIO pins.
Two PLLs to provide a fixed 48MHz clock for USB or ADC, and a flexible system clock up to 133MHz.
An internal Voltage Regulator to supply the core voltage so the end product only needs supply the IO voltage.
1.4. Pinout Reference
This section provides a quick reference for pinout and pin functions. Full details, including electrical specifications and
RP2040 Datasheet
1.3. The Chip 16