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Figure 29. An example
of fractional division.
All dividers support on-the-fly divisor changes meaning the output clock will switch cleanly from one divisor to another. So
the clock generator does not need to be stopped during clock divisor changes. It does this by synchronising the divisor
change to the end of the clock cycle. Similarly, the enable is synchronised to the end of the clock cycle so will not generate
glitches when the clock generator is enabled or disabled. Clock generators for always-on clocks are permanently enabled
and therefore do not have an enable control.
In the event that a clock generator locks up and never completes the current clock cycle it can be forced to stop using the
KILL control. This may result in an output glitch which may corrupt the logic driven by the clock. It is therefore
recommended the destination logic is reset prior to this operation. It is worth mentioning that this clock generator design
has been used in numerous chips and has never been known to lock up. The KILL control is inelegant and unnecessary
and should not be used as an alternative to the enable. Clock generators for always-on clocks are permanently active and
therefore do not have a KILL control.
2.14.3.3. Duty Cycle Correction
The divider operates on the rising edge of the input clock and so does not generate an even duty cycle clock when dividing
by odd numbers.
Divide by 3 will give a duty cycle of 33.3%, divide by 5 will be 40% etc. If enabled, the duty cycle correction logic will shift
the falling edge of the output clock to the falling edge of the input clock and restore a 50% duty cycle. The duty cycle
correction can be enabled and disabled while the clock is running. It will not operate when dividing by an even number.
Clock source
Generated clock
without DCC
Generated clock
with DCC
Figure 30. An example
of
duty_cycle_correction.
2.14.3.4. Clock Enables
Each clock goes to multiple destinations and, with a few exceptions, there are 2 enables for each destination. The WAKE_EN
registers are used to enable the clocks when the system is awake and the SLEEP_EN registers are used to enable the clocks
when the system is in sleep mode. The purpose of these enables is to reduce power in the clock distrbution networks for
components that are not being used. It is worth noting that a component which is not clocked will retain its configuration
so can be restarted quickly.
NOTE
The WAKE_EN and SLEEP_EN registers reset to 0x1, which means that by default all clocks are enabled. The programmer
only needs to use this feature if they desire a low-power design.
2.14.3.4.1. Clock Enable Exceptions
The cores do not have clock enables because they require a clock at all times to manage their own power saving features.
clk_sys_busfabric cannot be disabled in wake mode because that would prevent the cores from accessing any chip
registers, including those that control the clock enables.
RP2040 Datasheet
2.14. Clocks 166