Datasheet

ROSC frequency and adjust it accordingly. The reference could be the on-chip XOSC which can be turned on periodically
for this purpose. This may be useful in a very low power application where it is too costly to run the XOSC continuously
and too costly to use the PLLs to achieve high frequencies. If a time reference is available then the user should clock the
on-chip RTC from the ROSC and periodically compare it against the time reference, then adjust the ROSC frequency as
necessary. Using these techniques the ROSC frequency will drift due to VT variation so the user must take care that these
variations do not allow the ROSC frequency to drift out of the acceptable range.
2.14.2.1.5. Automatic overclocking using the ROSC
The datasheet maximum frequencies for any digital device are quoted for worst case PVT. Most chips in most normal
environments can run significantly faster than the quoted maximum and can therefore be overclocked. If the RP2040 is
running from the ROSC then both the ROSC and the digital components are similarly affected by PVT, so, as the ROSC
gets faster, the processors can also run faster. This means the user can overclock from the ROSC then rely on the ROSC
frequency tracking with PVT variations. The tracking of ROSC frequency and the processor capability is not perfect and
currently there is insufficient data to specify a safe ROSC setting for this mode of operation, so some experimentation is
required.
This mode of operation will maximise processor performance but will lead to variations in the time taken to complete a
task, which may be unacceptable in some applications. Also, if the user wants to use frequency sensitive interfaces such
as USB or UART then the XOSC and PLL must be used to provide a precise clock for those components.
2.14.2.2. Crystal Oscillator
The Crystal Oscillator provides a precise, stable clock reference and should be used where accurate timing is required and
no suitable external clocks are available. The frequency is determined by the external crystal and the oscillator supports
frequencies in the range 1MHz to 15MHz. The on-chip PLLs can be used to synthesise higher frequencies if required. The
reference design uses a 12MHz crystal. Using the XOSC and the PLLs, the on-chip components can be run at their
maximum frequencies. Appropriate margin is built into the design to tolerate up to 1000ppm variation in the XOSC
frequency.
The XOSC is inactive on power up. If required it must be enabled in software. XOSC startup takes several milliseconds and
the software must wait for the XOSC_STABLE flag to be set before starting the PLLs and before changing any clock
generators to use it. Prior to that the output from the XOSC may be non-existent or may have very short pulse widths
which will corrupt logic if used. Once it is running the reference clock (clk_ref) and the system clock (clk_sys) can be
switched to run from the XOSC and the ROSC can be stopped to save power.
The XOSC is not affected by SLEEP mode. It is automatically stopped and restarted in the same configuration when
entering and exiting DORMANT mode.
If the user wants to use the XOSC clock externally then it can be output to a GPIO pin using one of the clk_gpclk0-3
generators. It cannot be taken directly from the XIN or XOUT pins.
2.14.2.3. External Clocks
If adequate clocks exist in the application then they can be used to clock the RP2040 either on their own or in conjunction
with the XOSC or ROSC. This will potentially save power and will allow components on the RP2040 to be run
synchronously with external components to simplify data transfer between chips. External clocks can be input on the
GPIN0 & GPIN1 GPIO inputs and on the XIN input to the XOSC. If the XIN input is used in this way the XOSC must be
configured to pass through the XIN signal. All 3 inputs are limited to 50MHz but the on-chip PLLs can be used to
synthesise higher frequencies from the XIN input if required. If the frequency accuracy of the external clocks is poorer
than 1000ppm then the generated clocks should not be run at their maximum frequencies because they may exceed their
design margins.
Once the external clocks are running, the reference clock (clk_ref) and the system clock (clk_sys) can be switched to run
from the external clocks and the ROSC can be stopped to save power.
The external clock sources are not affected by SLEEP mode or DORMANT mode.
RP2040 Datasheet
2.14. Clocks 163