Datasheet

•
Ring Oscillator is started. rst_done is asserted once the ripple counter has seen a sufficient number of clock edges to
indicate the ring oscillator is stable
•
Crystal Oscillator reset is deasserted. The crystal oscillator is not started at this point, so rst_done is asserted
instantly.
•
clk_ref and clk_sys clock generators are taken out of reset. In the initial configuration clk_ref is running from the ring
oscillator with no divider. clk_sys is running from clk_ref. These clocks are needed for the rest of the sequence to
progress.
The rest of the sequence is fairly simple, with the following coming out of reset in order one by one:
•
Reset Controller - used to reset all non-boot peripherals
•
Chip-Level Reset and Voltage Regulator registers - used by the bootrom to check the boot state of the chip. In
particular, the PSM_RESTART_FLAG flag in the CHIP_RESET register can be set via SWD to indicate to the boot code that
there is bad code in flash and it should stop executing. The reset state of the CHIP_RESET register is determined by
the Chip-Level Reset subsystem and is not affected by reset coming from the power-on state machine
•
XIP (Execute-In-Place) - used by the bootrom to execute code from an external SPI flash
•
ROM and SRAM - Boot code is executed from the ROM. SRAM is used by processors and Bus Fabric.
•
Bus Fabric - Allows the processors to communicate with peripherals
•
Processor complex - Finally the processors can start running
The final thing to come out of reset is the processor complex. This includes both proc0 and proc1. Both processors will
start executing the bootcode from ROM. One of the first things the bootrom does is read the core id. At this point, proc1
will go to sleep leaving proc0 to continue with the bootrom execution. The processor complex has its own reset control
and various low-power modes which is why both the proc0 and proc1 resets come off at start of day, despite proc0 only
being needed for the bootrom.
2.12.3. Register Control
The power-on state machine is a fully automated piece of hardware. It requires no input from the user to work. There are
register controls that can be used to override and see the status of the power-on state machine for debugging. For
example, if a peripheral was stuck in reset and never asserted its rst_done signal the resets for all peripherals after it could
still be deasserted using the FRCE_ON register. There is also a WDSEL register which is used to decide what should be reset by
a Watchdog reset.
2.12.4. Interaction with Watchdog
The power-on state machine can be restarted from a software-programmable position if the Watchdog fires. For example,
in the case the processor is stuck in an infinite loop, or the programmer has somehow misconfigured the chip. It is
important to note that if a peripheral in the power-on state machine has the WDSEL bit set, every peripheral after it in the
power-on sequence will also be reset because the rst_done of the selected peripheral will be deasserted, asserting rst_n
for the remaining peripherals.
2.12.5. List of registers
Table 190. List of PSM
registers
Offset Name Info
0x0 FRCE_ON Force block out of reset (i.e. power it on)
0x4 FRCE_OFF Force into reset (i.e. power it off)
0x8 WDSEL Set to 1 if the watchdog should reset this
0xc DONE Is the subsystem ready?
RP2040 Datasheet
2.12. Power-On State Machine 153