Datasheet

Parameter Description Min Typ Max Units
t
BOD.ASSERT
brown-out
detection
assertion delay
3 10 μs
t
BOD.ENABLE
brown-out
detection enable
delay
35 55 μs
t
BOD.PROG
brown-out
detection
programming
delay
20 30 μs
2.11.4. Supply Monitor
The power-on and brown-out reset blocks are powered by the on-chip voltage regulator’s input supply (VREG_IOVDD). The
blocks are initialised when power is first applied, but may not be reliably re-initialised if power is removed and then
reapplied before VREG_IOVDD has dropped to a sufficiently low level. To prevent this happening, VREG_IOVDD is
monitored and the power-on reset block is re-initialised if it drops below the VREG_IOVDD activation threshold
(VREG_IOVDD
TH.ACTIVE
). VREG_IOVDD
TH.ACTIVE
is fixed at a nominal 1.1V, which should result in a threshold between 0.87V
and 1.26V. This threshold does not represent a safe operating voltage. It is the voltage that VREG_IOVDD must drop below
to reliably re-initialise the power-on reset block. For safe operation, VREG_IOVDD must be at a nominal voltage between
1.8V and 3.3V.
2.11.4.1. Detailed Specifications
Table 189. Voltage
Regulator Input Supply
Monitor Parameters
Parameter Description Min Typ Max Units
VREG_IOVDD
TH.ACTI
VE
VREG_IOVDD
activation
threshold
0.87 1.1 1.26 V
2.11.5. External Reset
The chip can also be reset by taking its RUN pin low. Taking RUN low will hold the chip in reset irrespective of the state of
the core power supply (DVDD) and the power-on reset / brown-out detection blocks. The chip will come out of reset as
soon as RUN is taken high, if all other reset sources have been released. RUN can be used to extend the initial power-on
reset, or can be driven from an external source to start and stop the chip as required. If RUN is not used, it should be tied
high.
2.11.6. Rescue Debug Port Reset
The chip can also be reset via the Rescue Debug Port. This allows the chip to be recovered from a locked up state. In
addition to resetting the chip, a Rescue Debug Port reset also sets the PSM_RESTART_FLAG in the CHIP_RESET register. This is
checked by the bootcode at startup, causing it to enter a safe state if the bit is set. See Section 2.3.4.2, “Rescue DP” for
more information.
2.11.7. Source of Last Reset
The source of the most recent chip-level reset can be determined by reading the state of the HAD_POR, HAD_RUN and
HAD_PSM_RESTART fields in the CHIP_RESET register. A one in the HAD_POR field indicates a power supply related reset, i.e.
RP2040 Datasheet
2.11. Chip-Level Reset 151