Datasheet

2.10.2. SLEEP State
RP2040 enters the SLEEP state when all of the following are true:
•
Both processors are asleep (e.g. in a WFE or WFI instruction)
•
The system DMA has no outstanding transfers on any channel
RP2040 exits the SLEEP state when either processor is awoken by an interrupt.
When in the SLEEP state, the top-level clock gates are masked by the SLEEP_ENx registers (<starting at SLEEP_EN0),
rather than the WAKE_ENx registers. This permits more aggressive pruning of the clock tree when the processors are
asleep.

NOTE
Though it is possible for a clock to be enabled during SLEEP and disabled outside of SLEEP, this is generally not useful
For example, if the system is sleeping until a character interrupt from a UART, the entire system except for the UART can
be clock-gated (SLEEP_ENx = all-zeroes except for CLK_SYS_UART0 and CLK_PERI_UART0). This includes system
infrastructure such as the bus fabric.
When the UART asserts its interrupt, and wakes a processor, RP2040 leaves SLEEP mode, and switches back to the
WAKE_ENx clock mask. At the minimum this should include the bus fabric, and the memory devices containing the
processor’s stack and interrupt vectors.
A system-level clock request handshake holds the processors off the bus until the clocks are re-enabled.
2.10.3. DORMANT State
The DORMANT state is a true zero-dynamic-power sleep state, where all clocks (and all oscillators) are disabled. The
system can awake from the DORMANT state upon a GPIO event (high/low level or rising/falling edge), or an RTC interrupt:
this restarts one of the oscillators (either ring oscillator or crystal oscillator), and ungates the oscillator output once it is
stable. System state is retained, so code execution resumes immediately upon leaving the DORMANT state.
Note that, if relying on the RTC (Section 4.9) to wake from the DORMANT state, the RTC must have some external clock
source. The RTC accepts clock frequencies as low as 1 Hz.
Note also that DORMANT does not halt PLLs. To avoid unnecessary power dissipation, software should power down PLLs
before entering the DORMANT state, and power up and reconfigure the PLLs again after exiting.
The DORMANT state is entered by writing a keyword to the DORMANT register in whichever oscillator is active (either ring
oscillator Ring Oscillator or crystal oscillator Crystal Oscillator). If both are active then the one providing the processor
clock must be stopped last because it will stop software from executing.
2.10.4. Memory Power Down
The main system memories (SRAM0…5, mapped to bus addresses 0x20000000 to 0x20041fff), as well as the USB DPRAM,
can be powered down via the MEMPOWERDOWN register in the Syscfg registers (see Syscfg). When powered down,
memories retain their current contents, but cannot be accessed. Static power is reduced.
RP2040 Datasheet
2.10. Power Control 145