Datasheet

2.9.7. Detailed Specifications
Table 186. Voltage
Regulator Detailed
Specifications
Parameter Description Min Typ Max Units
V
VREG_IOVDD
input supply
voltage
1.63 1.8 - 3.3 3.63 V
ΔV
VREG_VOUT
output voltage
variation
-3 +3 % of selected
output voltage
I
MAX
output current 100 mA
I
LIMIT
current limit 150 350 450 mA
ROK
TH.ASSERT
ROK assertion
threshold
87 90 93 % of selected
output voltage
ROK
TH.DEASSERT
ROK deassertion
threshold
84 87 90 % of selected
output voltage
t
POWER-ON
a
power-up time 275 350 μs
a
values will vary with load current and capacitance on VREG_VOUT. Conditions: EN = 1, load current = 0mA, VREG_IOVDD
ramps up in 100μs
2.10. Power Control
RP2040 provides a range of options for reducing dynamic power:
•
Top-level clock gating of individual peripherals and functional blocks
•
Automatic control of top-level clock gates based on processor sleep state
•
On-the-fly changes to system clock frequency or system clock source (e.g. switch to internal ring oscillator, and
disable PLLs and crystal oscillator)
•
Zero-dynamic-power DORMANT state, waking on GPIO event or RTC IRQ
All digital logic on RP2040 is in a single core power domain. The following options are available for static power reduction:
•
Placing memories into state-retaining power down state
•
Power gating on peripherals that support this, e.g. ADC, temperature sensor
2.10.1. Top-level Clock Gates
Each clock domain (for example, the system clock) may drive a large number of distinct hardware blocks, not all of which
may be required at once. To avoid unnecessary power dissipation, each individual endpoint of each clock (for example,
the UART system clock input) may be disabled at any time.
Enabling and disabling a clock gate is glitch-free. If a peripheral clock is temporarily disabled, and subsequently re-
enabled, the peripheral will be in the same state as prior to the clock being disabled. No reset or reinitialisation should be
required.
Clock gates are controlled by two sets of registers: the WAKE_ENx registers (starting at WAKE_EN0) and SLEEP_ENx
registers (starting at SLEEP_EN0). These two sets of registers are identical at the bit level, each possessing a flag to
control each clock endpoint. The WAKE_EN registers specify which clocks are enabled whilst the system is awake, and
the SLEEP_ENx registers select which clocks are enabled while the processor is in the SLEEP state (Section 2.10.2).
The two Cortex-M0+ processors do not have externally-controllable clock gates. Instead, the processors gate the clocks
of their subsystems autonomously, based on execution of WFI/WFE instructions, and external Event and IRQ signals.
RP2040 Datasheet
2.10. Power Control 144