Datasheet

After issuing the XIP exit sequence, the Bootrom attempts to read in the second stage from flash using standard 03h serial
read commands, which are near-universally supported. Since the Bootrom is immutable, it aims for compatibility rather
than performance.
2.7.2.3. Flash Second Stage
The flash second stage must configure the SSI and the external flash for the best possible execute-in-place performance.
This includes interface width, SCK frequency, SPI instruction prefix and an XIP continuation code for address-data only
modes. Generally some operation can be performed on the external flash so that it does not require an instruction prefix
on each access, and will simply respond to addresses with data.
Until the SSI is correctly configured for the attached flash device, it is not possible to access flash via the XIP address
window. Additionally, the Synopsys SSI can not be reconfigured at all without first disabling it. Therefore the second stage
must be copied from flash to SRAM by the bootrom, and executed in SRAM.
Alternatively, the second stage can simply shadow an image from external flash into SRAM, and not configure execute-in-
place.
This is the only job of the second stage. All other chip setup (e.g. PLLs, Voltage Regulator) can be performed by platform
initialisation code executed over the XIP interface, once the second stage has run.
2.7.2.3.1. Checksum
The last four bytes of the image loaded from flash (which we hope is a valid flash second stage) are a CRC32 checksum
of the first 252 bytes. The parameters of the checksum are:
•
Polynomial: 0x04c11db7
•
Input reflection: no
•
Output reflection: no
•
Initial value: 0xffffffff
•
Final XOR: 0x00000000
•
Checksum value appears as little-endian integer at end of image
The Bootrom makes 128 attempts of approximately 4ms each for a total of approximately 0.5 seconds before giving up
and dropping into USB code to load and checksum the second stage with varying SPI parameters. If it sees a checksum
pass it will immediately jump into the 252-byte payload which contains the flash second stage.
2.7.3. Bootrom Contents
Some of the bootrom is dedicated to the implementation of the boot sequence and USB boot interfaces. There is also
code in the bootrom useful to user programs. Table 158 shows the fixed memory layout of the first handful of words in
the Bootrom which are instrumental in locating other content within the bootrom.
Table 158. Bootrom
contents at fixed (well
known) addresses
Address Contents Description
0x00000000
32 bit pointer Initial boot stack pointer
0x00000004
32 bit pointer Pointer to boot reset handler function
0x00000008
32 bit pointer Pointer to boot NMI handler function
0x0000000c
32 bit pointer Pointer to boot Hard fault handler function
0x00000010
'M', 'u', 0x01
Magic
0x00000013
byte Bootrom version
0x00000014
16 bit pointer
Pointer to a public function lookup table (rom_func_table)
RP2040 Datasheet
2.7. Bootrom 116