Datasheet

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The debug host (which initiated the rescue) will provide further instruction.
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If watchdog scratch registers set to indicate pre-loaded code exists in SRAM, jump to that code
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Check if SPI CS pin is tied low ("bootrom button"), and skip flash boot if so.
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Set up IO muxing, pad controls on QSPI pins, and initialise Synopsys SSI for standard SPI mode
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Issue XIP exit sequence, in case flash is still in an XIP mode and has not been power-cycled
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Copy 256 bytes from SPI to internal SRAM (SRAM5) and check for valid CRC32 checksum
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If checksum passes, assume what we have loaded is a valid flash second stage
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Start executing the loaded code from SRAM (SRAM5)
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If no valid image found in SPI after 0.5 seconds of attempting to boot, drop to USB device boot
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USB device boot: appear as a USB Mass Storage Device
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Can program the SPI flash, or load directly into SRAM and run, by dragging and dropping an image in UF2
format.
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Also supports an extended PICOBOOT interface
2.7.2.1. Watchdog Boot
Watchdog boot allows users to install their own boot handler, and divert control away from the main boot sequence on
non-POR/BOR resets. It also simplifies running code over the JTAG test interface. It recognises the following values
written to the watchdog’s upper scratch registers:
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Scratch 4: magic number 0xb007c0d3
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Scratch 5: Entry point XORed with magic -0xb007c0d3 (0x4ff83f2d)
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Scratch 6: Stack pointer
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Scratch 7: Entry point
If either of the magic numbers mismatch, watchdog boot does not take place. If the numbers match, the Bootrom zeroes
scratch 4 before transferring control, so that the behaviour does not persist over subsequent reboots.
2.7.2.2. Flash Boot Sequence
One of the main challenges of a warm flash boot is forcing the external flash from XIP mode to a mode where it will
accept standard SPI commands. There is no standard method to discontinue XIP on an unknown flash. The Bootrom
provides a best-effort sequence with broad compatibility, which is as follows:
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CSn=1, IO[3:0]=4’b0000 (via pull downs to avoid contention), issue x32 clocks
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CSn=0, IO[3:0]=4’b1111 (via pull ups to avoid contention), issue x32 clocks
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CSn=1
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CSn=0, MOSI=1’b1 (driven low-Z, all other IOs Hi-Z), issue x16 clocks
This is designed to miss the XIP continuation codes on Cypress, Micron and Winbond parts. If the device is already in SPI
mode, it interprets this sequence as two FFh NOP instructions, which should be ignored.
As this is best effort only, there may be some devices which obstinately remain in XIP mode. There are then two options:
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Use a less efficient XIP mode where each transfer has an SPI instruction prefix, so the flash device remains
communicative in SPI mode.
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Boot code installs a compatible XIP exit sequence in SRAM, and configures the watchdog such that a warm boot will
jump straight into this sequence, foregoing our canned sequence.
RP2040 Datasheet
2.7. Bootrom 115