Datasheet

Table 153. CTR_HIT
Register
Bits Name Description Type Reset
31:0 NONAME A 32 bit saturating counter that increments upon each
cache hit,
i.e. when an XIP access is serviced directly from cached
data.
Write any value to clear.
WC 0x00000000
CTR_ACC Register
Description
Cache Access counter
Table 154. CTR_ACC
Register
Bits Name Description Type Reset
31:0 NONAME A 32 bit saturating counter that increments upon each XIP
access,
whether the cache is hit or not. This includes noncacheable
accesses.
Write any value to clear.
WC 0x00000000
STREAM_ADDR Register
Description
FIFO stream address
Table 155.
STREAM_ADDR
Register
Bits Name Description Type Reset
31:2 NONAME The address of the next word to be streamed from flash to
the streaming FIFO.
Increments automatically after each flash access.
Write the initial access address here before starting a
streaming read.
RW 0x00000000
1:0 Reserved. - - -
STREAM_CTR Register
Description
FIFO stream control
RP2040 Datasheet
2.5. Memory 112