Datasheet

2. The number of XIP accesses which resulted in a cache hit
For common use cases, this allows the cache hit rate to be profiled.
2.5.3.6. List of XIP Registers
Table 149. List of XIP
registers
Offset Name Info
0x00 CTRL Cache control
0x04 FLUSH Cache Flush control
0x08 STAT Cache Status
0x0c CTR_HIT Cache Hit counter
0x10 CTR_ACC Cache Access counter
0x14 STREAM_ADDR FIFO stream address
0x18 STREAM_CTR FIFO stream control
0x1c STREAM_FIFO FIFO stream data
CTRL Register
Description
Cache control
Table 150. CTRL
Register
Bits Name Description Type Reset
31:4 Reserved. - - -
3 POWER_DOWN When 1, the cache memories are powered down. They
retain state,
but can not be accessed. This reduces static power
dissipation.
Writing 1 to this bit forces CTRL_EN to 0, i.e. the cache
cannot
be enabled when powered down.
Cache-as-SRAM accesses will produce a bus error
response when
the cache is powered down.
RW 0x0
2 Reserved. - - -
1 ERR_BADWRITE When 1, writes to any alias other than 0x0 (caching,
allocating)
will produce a bus fault. When 0, these writes are silently
ignored.
In either case, writes to the 0x0 alias will deallocate on tag
match,
as usual.
RW 0x1
RP2040 Datasheet
2.5. Memory 110