Datasheet

Table Of Contents
2.5.3.2. Cache Flushing and Maintenance
The FLUSH register allows the entire cache contents to be flushed. This is necessary if software has reprogrammed the
flash contents, and needs to clear out stale data and code, without performing a reboot.
Flushing the cache whilst accessing flash data (perhaps initiating the flush on one core whilst another core may be
executing code from flash data) is a safe operation, but any master accessing flash data while the flush is in progress will
be stalled until completion. The flush is implemented by zeroing the cache tag memory using an internal counter, which
takes around 2000 clock cycles.
A complete cache flush dramatically slows subsequent code execution, until the cache "warms up" again. There is an
alternative, which allows cache contents corresponding to only a certain address range to be invalidated. A write to the
0x10… mirror will look up the addressed location in the cache, and delete any matching entry found. Writing to all word-
aligned locations in an address range (e.g. a flash sector that has just been erased and reprogrammed) therefore
eliminates the possibility of stale cached data in this range, without suffering the effects of a complete cache flush.
Pico Examples: https://github.com/raspberrypi/pico-examples/tree/pre_release/flash/cache_perfctr/flash_cache_perfctr.c Lines 30 - 55
30 // Flush cache to make sure we miss the first time we access test_data
31 xip_ctrl_hw->flush = 1;
32 while (!(xip_ctrl_hw->stat & XIP_STAT_FLUSH_READY_BITS))
33 tight_loop_contents();
34
35 // Clear counters (write any value to clear)
36 xip_ctrl_hw->ctr_acc = 1;
37 xip_ctrl_hw->ctr_hit = 1;
38
39 (void) *test_data_ptr;
40 check(xip_ctrl_hw->ctr_hit == 0 && xip_ctrl_hw->ctr_acc == 1,
41 "First access to data should miss");
42
43 (void) *test_data_ptr;
44 check(xip_ctrl_hw->ctr_hit == 1 && xip_ctrl_hw->ctr_acc == 2,
45 "Second access to data should hit");
46
47 // Write to invalidate individual cache lines (64 bits)
48 // Writes must be directed to the cacheable, allocatable alias (address 0x10.._....)
49 *test_data_ptr = 0;
50 (void) *test_data_ptr;
51 check(xip_ctrl_hw->ctr_hit == 1 && xip_ctrl_hw->ctr_acc == 3,
52 "Should miss after invalidation");
53 (void) *test_data_ptr;
54 check(xip_ctrl_hw->ctr_hit == 2 && xip_ctrl_hw->ctr_acc == 4,
55 "Second access after invalidation should hit again");
2.5.3.3. SSI
The execute-in-place functionality is provided by the SSI interface, documented in SSI. It supports 1, 2 or 4-bit SPI flash
interfaces (SPI, DSPI and QSPI), and can insert either an instruction prefix or mode continuation bits on each XIP access.
This includes the possibility of issuing a standard 03h serial flash read command for each access, allowing virtually any
serial flash device to be used. The maximum SPI clock frequency is half the system clock frequency.
The SSI can also be used as a standard FIFO-based SPI master, with DMA support. This mode is used by the bootrom to
extract the second stage bootloader from external flash (see Section 2.7.2). The bus interposer allows an atomic set, clear
or XOR operation to be posted to SSI control registers, in the same manner as other memory-mapped IO on RP2040. This
is described in more detail in Section 2.1.2.
RP2040 Datasheet
2.5. Memory 108