Datasheet

Figure 12. Flash
execute-in-place (XIP)
subsystem. System
accesses via the main
AHB-Lite slave are
decoded to determine
if they are XIP
accesses, direct
accesses to the SSI
e.g. for configuration,
or accesses to various
other hardware and
control registers in the
XIP subsystem. XIP
accesses are first
looked up in the
cache, to accelerate
accesses to recently-
used data. If the data
is not found in the
cache, an external
serial access is
generated via the SSI,
and the resulting data
is stored in the cache
and forwarded on to
the system bus.

NOTE
The serial flash interface is configured by the flash second stage when using the Pico SDK to run at an integer divider
of the system clock. All the included second stage boot implementations support a PICO_FLASH_SPI_CLKDIV setting (e.g.
defaulted to 4 in https://github.com/raspberrypi/pico-sdk/tree/pre_release/src/rp2_common/boot_stage2/
boot2_w25q080.S to make the default interface speed 125/4 = 31.25 MHz). This divider can be overridden by
specifying PICO_FLASH_SPI_CLKDIV in the particular board config header used with the Pico SDK.
2.5.3.1. XIP Cache
The cache is 16 kB, two way set-associative, 1 cycle hit. It is internal to the XIP subsystem, and only affects accesses to
XIP flash, so software does not have to consider cache coherence, unless performing flash programming operations. It
caches reads from a 24-bit flash address space, which is mirrored multiple times in the RP2040 address space, each alias
having different caching behaviour. The eight MSBs of the system address are used for segment decode, leaving 24 bits
for flash addressing, so the maximum supported flash size (for XIP operation) is 16MB. The available mirrors are:
•
0x10… XIP access, cacheable, allocating - Normal cache operation
•
0x11… XIP access, cacheable, non-allocating - Check for hit, don’t update cache on miss
•
0x12… XIP access, non-cacheable, allocating - Don’t check for hit, always update cache
•
0x13… XIP access, non-cacheable, non-allocating - Bypass cache completely
•
0x15… Use XIP cache as SRAM bank, mirrored across entire segment
If the cache is disabled, via the CTRL_EN register bit, then all four of the XIP aliases (0x10 to 0x13) will bypass the cache, and
access the flash directly. This has a significant impact on XIP code execution performance.
Access to the 0x15… segment produces a bus error unless the cache is disabled. Once the cache is disabled, this region
behaves as an additional 16 kB SRAM bank. Reads and writes are one cycle, but there is a wait state on consecutive write-
read sequences, i.e. there is no write forwarding buffer.
RP2040 Datasheet
2.5. Memory 107