Datasheet

Bits Name Description Type Reset
4 VALID On writes, indicates whether the write must update the
base address of the region identified by the REGION field,
updating the MPU_RNR to indicate this new region.
Write:
0 = MPU_RNR not changed, and the processor:
Updates the base address for the region specified in the
MPU_RNR.
Ignores the value of the REGION field.
1 = The processor:
Updates the value of the MPU_RNR to the value of the
REGION field.
Updates the base address for the region specified in the
REGION field.
Always reads as zero.
RW 0x0
3:0 REGION On writes, specifies the number of the region whose base
address to update provided VALID is set written as 1. On
reads, returns bits [3:0] of MPU_RNR.
RW 0x0
MPU_RASR Register
Description
Use the MPU Region Attribute and Size Register to define the size, access behaviour and memory type of the region
identified by MPU_RNR, and enable that region.
Table 147. MPU_RASR
Register
Bits Name Description Type Reset
31:16 ATTRS The MPU Region Attribute field. Use to define the region
attribute control.
28 = XN: Instruction access disable bit:
0 = Instruction fetches enabled.
1 = Instruction fetches disabled.
26:24 = AP: Access permission field
18 = S: Shareable bit
17 = C: Cacheable bit
16 = B: Bufferable bit
RW 0x0000
15:8 SRD Subregion Disable. For regions of 256 bytes or larger, each
bit of this field controls whether one of the eight equal
subregions is enabled.
RW 0x00
7:6 Reserved. - - -
5:1 SIZE Indicates the region size. Region size in bytes = 2^(SIZE+1).
The minimum permitted value is 7 (b00111) = 256Bytes
RW 0x00
0 ENABLE Enables the region. RW 0x0
2.5. Memory
RP2040 has embedded ROM and SRAM, and access to external Flash via a QSPI interface. Details of internal memory are
given below.
RP2040 Datasheet
2.5. Memory 104