Datasheet

Bits Name Description Type Reset
2 PRIVDEFENA Controls whether the default memory map is enabled as a
background region for privileged accesses. This bit is
ignored when ENABLE is clear.
0 = If the MPU is enabled, disables use of the default
memory map. Any memory access to a location not
covered by any enabled region causes a fault.
1 = If the MPU is enabled, enables use of the default
memory map as a background region for privileged
software accesses.
When enabled, the background region acts as if it is region
number -1. Any region that is defined and enabled has
priority over this default map.
RW 0x0
1 HFNMIENA Controls the use of the MPU for HardFaults and NMIs.
Setting this bit when ENABLE is clear results in
UNPREDICTABLE behaviour.
When the MPU is enabled:
0 = MPU is disabled during HardFault and NMI handlers,
regardless of the value of the ENABLE bit.
1 = the MPU is enabled during HardFault and NMI handlers.
RW 0x0
0 ENABLE Enables the MPU. If the MPU is disabled, privileged and
unprivileged accesses use the default memory map.
0 = MPU disabled.
1 = MPU enabled.
RW 0x0
MPU_RNR Register
Description
Use the MPU Region Number Register to select the region currently accessed by MPU_RBAR and MPU_RASR.
Table 145. MPU_RNR
Register
Bits Name Description Type Reset
31:4 Reserved. - - -
3:0 REGION Indicates the MPU region referenced by the MPU_RBAR
and MPU_RASR registers.
The MPU supports 8 memory regions, so the permitted
values of this field are 0-7.
RW 0x0
MPU_RBAR Register
Description
Read the MPU Region Base Address Register to determine the base address of the region identified by MPU_RNR.
Write to update the base address of said region or that of a specified region, with whose number MPU_RNR will also
be updated.
Table 146. MPU_RBAR
Register
Bits Name Description Type Reset
31:8 ADDR Base address of the region. RW 0x000000
7:5 Reserved. - - -
RP2040 Datasheet
2.4. Cortex-M0+ 103