Datasheet

Bits Name Description Type Reset
23:22 PRI_14 Priority of system handler 14, PendSV RW 0x0
21:0 Reserved. - - -
SHCSR Register
Description
Use the System Handler Control and State Register to determine or clear the pending status of SVCall.
Table 142. SHCSR
Register
Bits Name Description Type Reset
31:16 Reserved. - - -
15 SVCALLPENDED Reads as 1 if SVCall is Pending. Write 1 to set pending
SVCall, write 0 to clear pending SVCall.
RW 0x0
14:0 Reserved. - - -
MPU_TYPE Register
Description
Read the MPU Type Register to determine if the processor implements an MPU, and how many regions the MPU
supports.
Table 143. MPU_TYPE
Register
Bits Name Description Type Reset
31:24 Reserved. - - -
23:16 IREGION Instruction region. Reads as zero as ARMv6-M only
supports a unified MPU.
RO 0x00
15:8 DREGION Number of regions supported by the MPU. RO 0x08
7:1 Reserved. - - -
0 SEPARATE Indicates support for separate instruction and data address
maps. Reads as 0 as ARMv6-M only supports a unified
MPU.
RO 0x0
MPU_CTRL Register
Description
Use the MPU Control Register to enable and disable the MPU, and to control whether the default memory map is
enabled as a background region for privileged accesses, and whether the MPU is enabled for HardFaults and NMIs.
Table 144. MPU_CTRL
Register
Bits Name Description Type Reset
31:3 Reserved. - - -
RP2040 Datasheet
2.4. Cortex-M0+ 102