Datasheet

Bits Name Description Type Reset
31:16 VECTKEY Register key:
Reads as Unknown
On writes, write 0x05FA to VECTKEY, otherwise the write is
ignored.
RW 0x0000
15 ENDIANESS Data endianness implemented:
0 = Little-endian.
RO 0x0
14:3 Reserved. - - -
2 SYSRESETREQ Writing 1 to this bit causes the SYSRESETREQ signal to the
outer system to be asserted to request a reset. The
intention is to force a large system reset of all major
components except for debug. The C_HALT bit in the
DHCSR is cleared as a result of the system reset
requested. The debugger does not lose contact with the
device.
RW 0x0
1 VECTCLRACTIVE Clears all active state information for fixed and
configurable exceptions. This bit: is self-clearing, can only
be set by the DAP when the core is halted. When set: clears
all active exception status of the processor, forces a return
to Thread mode, forces an IPSR of 0. A debugger must re-
initialize the stack.
RW 0x0
0 Reserved. - - -
SCR Register
Description
System Control Register. Use the System Control Register for power-management functions: signal to the system
when the processor can enter a low power state, control how the processor enters and exits low power states.
Table 138. SCR
Register
Bits Name Description Type Reset
31:5 Reserved. - - -
4 SEVONPEND Send Event on Pending bit:
0 = Only enabled interrupts or events can wakeup the
processor, disabled interrupts are excluded.
1 = Enabled events and all interrupts, including disabled
interrupts, can wakeup the processor.
When an event or interrupt becomes pending, the event
signal wakes up the processor from WFE. If the
processor is not waiting for an event, the event is
registered and affects the next WFE.
The processor also wakes up on execution of an SEV
instruction or an external event.
RW 0x0
3 Reserved. - - -
2 SLEEPDEEP Controls whether the processor uses sleep or deep sleep
as its low power mode:
0 = Sleep.
1 = Deep sleep.
RW 0x0
RP2040 Datasheet
2.4. Cortex-M0+ 100