Datasheet

Bits Name Description Type Reset
26 PENDSTSET SysTick exception set-pending bit.
Write:
0 = No effect.
1 = Changes SysTick exception state to pending.
Read:
0 = SysTick exception is not pending.
1 = SysTick exception is pending.
RW 0x0
25 PENDSTCLR SysTick exception clear-pending bit.
Write:
0 = No effect.
1 = Removes the pending state from the SysTick exception.
This bit is WO. On a register read its value is Unknown.
RW 0x0
24 Reserved. - - -
23 ISRPREEMPT The system can only access this bit when the core is
halted. It indicates that a pending interrupt is to be taken in
the next running cycle. If C_MASKINTS is clear in the Debug
Halting Control and Status Register, the interrupt is
serviced.
RO 0x0
22 ISRPENDING External interrupt pending flag RO 0x0
21 Reserved. - - -
20:12 VECTPENDING Indicates the exception number for the highest priority
pending exception: 0 = no pending exceptions. Non zero =
The pending state includes the effect of memory-mapped
enable and mask registers. It does not include the
PRIMASK special-purpose register qualifier.
RO 0x000
11:9 Reserved. - - -
8:0 VECTACTIVE Active exception number field. Reset clears the
VECTACTIVE field.
RO 0x000
VTOR Register
Description
The VTOR holds the vector table offset address.
Table 136. VTOR
Register
Bits Name Description Type Reset
31:8 TBLOFF Bits [31:8] of the indicate the vector table offset address. RW 0x000000
7:0 Reserved. - - -
AIRCR Register
Description
Use the Application Interrupt and Reset Control Register to: determine data endianness, clear all active state
information from debug halt mode, request a system reset.
Table 137. AIRCR
Register
RP2040 Datasheet
2.4. Cortex-M0+ 99