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RP2040 Datasheet Colophon Copyright © 2020 Raspberry Pi (Trading) Ltd. The documentation of the RP2040 microcontroller is licensed under a Creative Commons Attribution-NoDerivatives 4.0 International (CC BY-ND). Portions Copyright © 2019 Synopsys, Inc. All rights reserved. Used with permission. Synopsys & DesignWare are registered trademarks of Synopsys, Inc. Portions Copyright © 2000-2001, 2005, 2007, 2009, 2011-2012, 2016 ARM Limited. All rights reserved. Used with permission.
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RP2040 Datasheet HIGH RISK ACTIVITIES.
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RP2040 Datasheet Table of Contents Colophon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 IP Contributors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Legal Disclaimer Notice . . . . . . . . . . . . . . . . . . . .
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RP2040 Datasheet 2.4.2.7. Single-cycle I/O port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 2.4.2.8. Power Management Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 2.4.2.8.1. Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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RP2040 Datasheet 2.7.4.2. UF2 Format Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7.5. USB PICOBOOT Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7.5.1. Identifying The Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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RP2040 Datasheet 2.11.6. Rescue Debug Port Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.11.7. Source of Last Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.11.8. List of Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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RP2040 Datasheet 2.17.3. Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.17.4. List of registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.18. GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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RP2040 Datasheet 3.4.4.1. Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.4.2. Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.4.3. Assembler Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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RP2040 Datasheet 4.1.1.1.1. Device Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.1.1.2. Host Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.2. Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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RP2040 Datasheet 4.3.2.6. Transmit logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.2.7. Receive logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.2.8. Interrupt generation logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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RP2040 Datasheet 4.4.10.1.4. Slave-Transfer Operation For Bulk Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.10.2. Master Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.10.2.1. Initial Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.10.2.2.
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RP2040 Datasheet 4.6.2.1. Pulse Width Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.2.2. 0% and 100% Duty Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.2.3. Double Buffering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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RP2040 Datasheet 4.10.5. List of Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.11. SSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.11.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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RP2040 Datasheet Standard types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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RP2040 Datasheet Chapter 1. Introduction RP2040 is a low cost microcontroller device with the quality, cost and simplicity of the Raspberry Pi. Much like the Raspberry Pi is an accessible computer, the RP2040 is an accessible chip with everything you need to build a product. The RP2040 is supported with both C/C++ and MicroPython cross-platform development environments, including easy access to runtime debugging. It has UF2 boot and floating-point routines baked into the chip.
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RP2040 Datasheet • USB 1.1 Host/Device 1.3. The Chip RP2040 has a dual M0+ processor cores, DMA, internal memory and peripheral blocks connected via AHB/APB bus fabric. Figure 2. A system overview of the RP2040 chip Code may be executed directly from external memory through a dedicated SPI, DSPI or QSPI interface. A small cache improves performance for typical applications. Debug is available via the SWD interface.
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RP2040 Datasheet package drawings, can be found in Chapter 5. 1.4.1. Pin Locations Figure 3.
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RP2040 Datasheet Name Description TESTEN Factory test mode pin. Tie to GND. GND Single external ground connection, bonded to a number of internal ground pads on the RP2040 die. IOVDD Power supply for digital GPIOs, nominal voltage 1.8 V to 3.3 V USB_IOVDD Power supply for internal USB Full Speed PHY, nominal voltage 3.3 V ADC_IOVDDD Power supply for analogue-to-digital converter, nominal voltage 3.3 V VREG_IOVDD Power input for the internal core voltage regulator, nominal voltage 1.8 V to 3.
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RP2040 Datasheet 10 SPI1 SCK UART1 I2C1 SDA PWM5 A SIO PIO0 PIO1 USB VBUS CTS 11 SPI1 TX UART1 DET I2C1 SCL PWM5 B SIO PIO0 PIO1 USB VBUS RTS 12 SPI1 RX EN UART0 TX I2C0 SDA PWM6 A SIO PIO0 PIO1 USB OVCUR DET 13 SPI1 CSn UART0 RX I2C0 SCL PWM6 B SIO PIO0 PIO1 USB VBUS DET 14 SPI1 SCK UART0 I2C1 SDA PWM7 A SIO PIO0 PIO1 USB VBUS CTS 15 SPI1 TX UART0 EN I2C1 SCL PWM7 B SIO PIO0 PIO1 USB RTS OVCUR DET 16 SPI0 RX UART0 TX I2C0 SDA PWM0 A SIO PIO0 PIO
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RP2040 Datasheet Table 2. GPIO bank 0 function descriptions Function Name Description SPIx Connect one of the internal PL022 SPI peripherals to GPIO UARTx Connect one of the internal PL011 UART peripherals to GPIO I2Cx Connect one of the internal DW I2C peripherals to GPIO PWMx A/B Connect a PWM slice to GPIO. There are eight PWM slices, each with two output channels (A/B). The B pin can also be used as an input, for frequency and duty cycle measurement.
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RP2040 Datasheet Chapter 2. System Description This chapter describes the RP2040 key system features including processor, memory, how blocks are connected, clocks, resets, power, and IO. Refer to Figure 2 for an overview diagram. 2.1. Bus Fabric The RP2040 bus fabric routes addresses and data across the chip. Figure 4 shows the high-level structure of the bus fabric.
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RP2040 Datasheet GB/s. The system address map has been arranged to make this parallel bandwidth available to as many software use cases as possible — for example, the striped SRAM alias (SRAM) scatters main memory accesses across four crossbar ports (SRAM0…3), so that more memory accesses can proceed in parallel. 2.1.1. AHB-Lite Crossbar At the centre of the RP2040 bus fabric is a 4:10 fully-connected crossbar.
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RP2040 Datasheet  NOTE Priority arbitration only applies to multiple masters attempting to access the same slave on the same cycle. Accesses to different slaves, e.g. different SRAM banks, can proceed simultaneously. When accessing a slave with zero wait states, such as SRAM (i.e. can be accessed once per system clock cycle), highpriority masters will never observe any slowdown or other timing effects caused by accesses from low-priority masters.
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RP2040 Datasheet PERFSEL Event Description x 16 XIP_MAIN access, Completion of an access to the XIP_MAIN arbiter, which was previously delayed due to contested an access by another master. 17 XIP_MAIN access Completion of an access to the XIP_MAIN arbiter 18 ROM access, Completion of an access to the ROM arbiter, which was previously delayed due to an contested access by another master. ROM access Completion of an access to the ROM arbiter 19 2.1.2.
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RP2040 Datasheet set/clear/XOR (see Section 2.1.2). Note that this is more flexible than byte or halfword writes, as any combination of fields can be updated in one operation. Upon a 8-bit or 16-bit write (such as a strb instruction on the Cortex-M0+), an IO register will sample the entire 32-bit write databus. The Cortex-M0+ and DMA on RP2040 will always replicate narrow data across the bus: Pico Examples: https://github.
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RP2040 Datasheet Offset Name Info 0x0c PERFSEL0 Bus fabric performance event select for PERFCTR0 0x10 PERFCTR1 Bus fabric performance counter 1 0x14 PERFSEL1 Bus fabric performance event select for PERFCTR1 0x18 PERFCTR2 Bus fabric performance counter 2 0x1c PERFSEL2 Bus fabric performance event select for PERFCTR2 0x20 PERFCTR3 Bus fabric performance counter 3 0x24 PERFSEL3 Bus fabric performance event select for PERFCTR3 BUS_PRIORITY Register Description Set the priority of each m
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RP2040 Datasheet Table 6. PERFCTR0 Register Bits Name Description Type Reset 31:24 Reserved. - - - 23:0 NONAME Busfabric saturating performance counter 0 WC 0x000000 Count some event signal from the busfabric arbiters. Write any value to clear. Select an event to count using PERFSEL0 PERFSEL0 Register Description Bus fabric performance event select for PERFCTR0 Table 7. PERFSEL0 Register Bits Name Description Type Reset 31:5 Reserved.
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RP2040 Datasheet Table 10. PERFCTR2 Register Bits Name Description Type Reset 31:24 Reserved. - - - 23:0 NONAME Busfabric saturating performance counter 2 WC 0x000000 Count some event signal from the busfabric arbiters. Write any value to clear. Select an event to count using PERFSEL2 PERFSEL2 Register Description Bus fabric performance event select for PERFCTR2 Table 11. PERFSEL2 Register Bits Name Description Type Reset 31:5 Reserved.
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RP2040 Datasheet APB Peripherals 0x40000000 AHB-Lite Peripherals 0x50000000 IOPORT Registers 0xd0000000 Cortex-M0+ internal registers 0xe0000000 2.2.2. Detail ROM: ROM_BASE 0x00000000 XIP: XIP_BASE 0x10000000 XIP_NOALLOC_BASE 0x11000000 XIP_NOCACHE_BASE 0x12000000 XIP_NOCACHE_NOALLOC_BASE 0x13000000 XIP_CTRL_BASE 0x14000000 XIP_SRAM_BASE 0x15000000 XIP_SRAM_END 0x15004000 XIP_SSI_BASE 0x18000000 SRAM.
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RP2040 Datasheet CLOCKS_BASE 0x40008000 RESETS_BASE 0x4000c000 PSM_BASE 0x40010000 IO_BANK0_BASE 0x40014000 IO_QSPI_BASE 0x40018000 PADS_BANK0_BASE 0x4001c000 PADS_QSPI_BASE 0x40020000 XOSC_BASE 0x40024000 PLL_SYS_BASE 0x40028000 PLL_USB_BASE 0x4002c000 BUSCTRL_BASE 0x40030000 UART0_BASE 0x40034000 UART1_BASE 0x40038000 SPI0_BASE 0x4003c000 SPI1_BASE 0x40040000 I2C0_BASE 0x40044000 I2C1_BASE 0x40048000 ADC_BASE 0x4004c000 PWM_BASE 0x40050000 TIMER_BASE 0x40054000 WAT
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RP2040 Datasheet IOPORT Peripherals: 0xd0000000 SIO_BASE Cortex-M0+ Internal Peripherals: 0xe0000000 PPB_BASE 2.3. Processor subsystem The RP2040 processor subsystem consists of two Arm Cortex-M0+ processors — each with its standard internal Arm CPU peripherals — alongside external peripherals for GPIO access and inter-core communication. Details of the Arm Cortex-M0+ processors, including the specific feature configuration used on RP2040, can be found in Cortex-M0+. Figure 6.
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RP2040 Datasheet Figure 7. The singlecycle IO block contains memory- Core 0 Core 1 mapped hardware which the processors must be able to Single-cycle IO IOPORT IOPORT access quickly. The FIFOs and spinlocks CPUID 1 CPUID 0 support message passing and synchronisation FIFO 0 to 1 between the two cores. The shared GPIO registers provide FIFO 1 to 0 fast and concurrencysafe direct access to GPIO-capable pins.
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RP2040 Datasheet  NOTE To drive a pin with the SIO’s GPIO registers, the GPIO multiplexer for this pin must first be configured to select the SIO GPIO function. See Table 274. These GPIO registers are shared between the two cores, and both cores can access them simultaneously.
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RP2040 Datasheet  NOTE This is a conceptual model for the result that is produced when two cores write to a GPIO register simultaneously. The register does not actually contain this intermediate value at any point. In the previous example, if the pin is initially 0, and core 0 performs a SET while core 1 performs a XOR, the GPIO output remains low without any positive glitch. 2.3.1.3.
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RP2040 Datasheet 2.3.1.5. Integer Divider The SIO provides one 8-cycle signed/unsigned divide/modulo module to each of the cores. Calculation is started by writing a dividend and divisor to the two argument registers, DIVIDEND and DIVISOR. The divider calculates the quotient / and remainder % of this division over the next 8 cycles, and on the 9th cycle the results can be read from the two result registers DIV_QUOTIENT and DIV_REMAINDER.
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RP2040 Datasheet  NOTE A new calculation begins immediately with every write to an operand register, and a new operand write immediately squashes any calculation currently in progress. For example, when dividing many numbers by the same divisor, only xDIVIDEND needs to be written, and the signedness of each calculation is determined by whether SDIVIDEND or UDIVIDEND is written. To support save and restore on interrupt handler entry/exit (or on e.g.
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RP2040 Datasheet Figure 8. An interpolator. The two accumulator registers Base 0 and three base registers have singlecycle read/write Result 0 0 processor. The 0 Accumulator 0 access from the Result 1 1 1 organised into two masking, shifting and accumulators.
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RP2040 Datasheet Figure 9. Each lane of each interpolator can be configured to Result 0 0 perform mask, shift and sign-extension on 0 Accumulator 0 Result 1 1 Right Shift Mask 1 Sign-extend fromMask Accumulator 1 one of the 1 0 1 0 Add to BASE1 (for PEEK0/POP0) Add to BASE2 accumulators. This is (forms part of fed into adders which PEEK2/POP2) produces final results, which may optionally be fed back into the accumulators with each read.
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RP2040 Datasheet ACCUM0 = 1234abcd Nibble 0: 0000000d Nibble 1: 000000c0 Nibble 2: 00000b00 Nibble 3: 0000a000 Nibble 4: 00040000 Nibble 5: 00300000 Nibble 6: 02000000 Nibble 7: 10000000 Masking with sign extension: Nibble 0: fffffffd Nibble 1: ffffffc0 Nibble 2: fffffb00 Nibble 3: ffffa000 Nibble 4: 00040000 Nibble 5: 00300000 Nibble 6: 02000000 Nibble 7: 10000000 Changing the result and input multiplexers can create feedback between the accumulators. This is useful e.g. for audio dithering.
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RP2040 Datasheet 2.3.1.6.2. Blend Mode Blend mode is available on INTERP0 on each core, and is enabled by the CTRL_LANE0_BLEND control flag. It performs linear interpolation, which we define as follows: Where is the register BASE0, is the register BASE1, and is a fractional value formed from the least significant 8 bits of the lane 1 shift and mask value.
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RP2040 Datasheet Pico Examples: https://github.com/raspberrypi/pico-examples/tree/pre_release/interp/hello_interp/hello_interp.
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RP2040 Datasheet Pico Examples: https://github.com/raspberrypi/pico-examples/tree/pre_release/interp/hello_interp/hello_interp.
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RP2040 Datasheet 203 interp1->accum[0] = i; 204 205 printf("%d\t%d\n", i, (int) interp1->peek[0]); } 206 } This should print: -1024 0 -768 0 -512 0 -256 0 0 0 256 64 512 128 768 192 1024 255 2.3.1.6.4.
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RP2040 Datasheet 172 173 interp0->accum[0] = 0; // initial sample_offset; 174 interp0->base[2] = (uintptr_t) samples; 175 for (int i = 0; i < 16; i++) { 176 // result2 = samples + (lane0 raw result) 177 // i.e. ptr to the first of two samples to blend between 178 int16_t *sample_pair = (int16_t *) interp0->peek[2]; 179 interp0->base[0] = sample_pair[0]; 180 interp0->base[1] = sample_pair[1]; 181 printf("%d\t(%d%% between %d and %d)\n", (int) interp0->peek[1], 182 100 * (interp0->add_raw[
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RP2040 Datasheet 217 interp_set_config(interp0, 0, &cfg); 218 219 interp_config_shift(&cfg, uv_fractional_bits - texture_width_bits); 220 interp_config_mask(&cfg, texture_width_bits, texture_width_bits + texture_height_bits 1); 221 interp_set_config(interp0, 1, &cfg); 222 223 interp0->base[2] = (uintptr_t) texture; 224 } 225 226 void texture_mapped_span(uint8_t *output, uint32_t u, uint32_t v, uint32_t du, uint32_t dv, uint count) { 227 // u, v are texture coordinates in fixed point with uv_frac
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RP2040 Datasheet 0x01 0x12 0x12 0x13 0x23 0x20 0x20 0x31 0x31 TODO: GRAHAM: Any other sample use cases? 2.3.1.7. List of Registers Table 15.
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RP2040 Datasheet Offset Name Info 0x06c DIV_SDIVISOR Divider signed divisor 0x070 DIV_QUOTIENT Divider result quotient 0x074 DIV_REMAINDER Divider result remainder 0x078 DIV_CSR Control and status register for divider. 0x080 INTERP0_ACCUM0 Read/write access to accumulator 0 0x084 INTERP0_ACCUM1 Read/write access to accumulator 1 0x088 INTERP0_BASE0 Read/write access to BASE0 register. 0x08c INTERP0_BASE1 Read/write access to BASE1 register.
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RP2040 Datasheet Offset Name Info 0x0ec INTERP1_CTRL_LANE0 Control register for lane 0 0x0f0 INTERP1_CTRL_LANE1 Control register for lane 1 0x0f4 INTERP1_ACCUM0_ADD Values written here are atomically added to ACCUM0 0x0f8 INTERP1_ACCUM1_ADD Values written here are atomically added to ACCUM1 0x0fc INTERP1_BASE_1AND0 On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.
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RP2040 Datasheet Offset Name 0x178 SPINLOCK30 0x17c SPINLOCK31 Info CPUID Register Description Processor core identifier Table 16. CPUID Register Bits Name Description Type Reset 31:0 NONAME Value is 0 when read from processor core 0, and 1 when RO - read from processor core 1. GPIO_IN Register Description Input value for GPIO pins Table 17. GPIO_IN Register Bits Name Description Type Reset 31:30 Reserved.
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RP2040 Datasheet Table 19. GPIO_OUT Register Bits Name Description Type Reset 31:30 Reserved. - - - 29:0 NONAME Set output level (1/0 -> high/low) for GPIO0…29. RW 0x00000000 Reading back gives the last value written, NOT the input value from the pins. If core 0 and core 1 both write to GPIO_OUT simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result.
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RP2040 Datasheet Table 23. GPIO_OE Register Bits Name Description Type Reset 31:30 Reserved. - - - 29:0 NONAME Set output enable (1/0 -> output/input) for GPIO0…29. RW 0x00000000 Reading back gives the last value written. If core 0 and core 1 both write to GPIO_OE simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result.
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RP2040 Datasheet Table 27. GPIO_HI_OUT Register Bits Name Description Type Reset 31:6 Reserved. - - - 5:0 NONAME Set output level (1/0 -> high/low) for QSPI IO0…5. RW 0x00 Reading back gives the last value written, NOT the input value from the pins. If core 0 and core 1 both write to GPIO_HI_OUT simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result.
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RP2040 Datasheet Table 31. GPIO_HI_OE Register Bits Name Description Type Reset 31:6 Reserved. - - - 5:0 NONAME Set output enable (1/0 -> output/input) for QSPI IO0…5. RW 0x00 Reading back gives the last value written. If core 0 and core 1 both write to GPIO_HI_OE simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result.
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RP2040 Datasheet Bits Name Description Type Reset 3 ROE Sticky flag indicating the RX FIFO was read when empty. WC 0x0 WC 0x0 RO 0x1 Value is 1 if this core’s RX FIFO is not empty (i.e. if FIFO_RD RO 0x0 This read was ignored by the FIFO. 2 WOF Sticky flag indicating the TX FIFO was written when full. This write was ignored by the FIFO. 1 RDY Value is 1 if this core’s TX FIFO is not full (i.e.
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RP2040 Datasheet Description Divider unsigned divisor Write to the DIVISOR operand of the divider, i.e. the q in p / q. Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER. UDIVIDEND/SDIVIDEND are aliases of the same internal register. The U alias starts an unsigned calculation, and the S alias starts a signed calculation. Table 40.
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RP2040 Datasheet Table 44. DIV_REMAINDER Register Bits Name 31:0 NONAME Description Type Reset RW 0x00000000 DIV_CSR Register Description Control and status register for divider. Table 45. DIV_CSR Register Bits Name Description Type Reset 31:2 Reserved. - - - 1 DIRTY Changes to 1 when any register is written, and back to 0 RO 0x0 RO 0x1 Type Reset RW 0x00000000 Type Reset RW 0x00000000 when QUOTIENT is read.
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RP2040 Datasheet Table 48. INTERP0_BASE0 Register Bits Name 31:0 NONAME Description Type Reset RW 0x00000000 Type Reset RW 0x00000000 Type Reset RW 0x00000000 Type Reset RO 0x00000000 Type Reset RO 0x00000000 Type Reset RO 0x00000000 INTERP0_BASE1 Register Description Read/write access to BASE1 register. Table 49. INTERP0_BASE1 Register Bits Name 31:0 NONAME Description INTERP0_BASE2 Register Description Read/write access to BASE2 register. Table 50.
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RP2040 Datasheet Table 54. INTERP0_PEEK_LANE 0 Register Bits Name 31:0 NONAME Description Type Reset RO 0x00000000 Type Reset RO 0x00000000 Type Reset RO 0x00000000 INTERP0_PEEK_LANE1 Register Description Read LANE1 result, without altering any internal state (PEEK). Table 55. INTERP0_PEEK_LANE 1 Register Bits Name 31:0 NONAME Description INTERP0_PEEK_FULL Register Description Read FULL result, without altering any internal state (PEEK). Table 56.
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RP2040 Datasheet Bits Name Description Type Reset 17 CROSS_RESULT If 1, feed the opposite lane’s result into this lane’s RW 0x0 RW 0x0 If SIGNED is set, the shifted and masked accumulator value RW 0x0 accumulator on POP. 16 CROSS_INPUT If 1, feed the opposite lane’s accumulator into this lane’s shift + mask hardware.
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RP2040 Datasheet INTERP0_ACCUM0_ADD Register Description Values written here are atomically added to ACCUM0 Reading yields lane 0’s raw shift and mask value (BASE0 not added). Table 59. INTERP0_ACCUM0_AD D Register Bits Name Description Type Reset 31:24 Reserved. - - - 23:0 NONAME RW 0x000000 INTERP0_ACCUM1_ADD Register Description Values written here are atomically added to ACCUM1 Reading yields lane 1’s raw shift and mask value (BASE1 not added). Table 60.
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RP2040 Datasheet Table 64. INTERP1_BASE0 Register Bits Name 31:0 NONAME Description Type Reset RW 0x00000000 Type Reset RW 0x00000000 Type Reset RW 0x00000000 Type Reset RO 0x00000000 Type Reset RO 0x00000000 Type Reset RO 0x00000000 INTERP1_BASE1 Register Description Read/write access to BASE1 register. Table 65. INTERP1_BASE1 Register Bits Name 31:0 NONAME Description INTERP1_BASE2 Register Description Read/write access to BASE2 register. Table 66.
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RP2040 Datasheet Table 70. INTERP1_PEEK_LANE 0 Register Bits Name 31:0 NONAME Description Type Reset RO 0x00000000 Type Reset RO 0x00000000 Type Reset RO 0x00000000 INTERP1_PEEK_LANE1 Register Description Read LANE1 result, without altering any internal state (PEEK). Table 71. INTERP1_PEEK_LANE 1 Register Bits Name 31:0 NONAME Description INTERP1_PEEK_FULL Register Description Read FULL result, without altering any internal state (PEEK). Table 72.
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RP2040 Datasheet Bits Name Description Type Reset 16 CROSS_INPUT If 1, feed the opposite lane’s accumulator into this lane’s RW 0x0 If SIGNED is set, the shifted and masked accumulator value RW 0x0 shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass) 15 SIGNED is sign-extended to 32 bits before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor.
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RP2040 Datasheet Description Values written here are atomically added to ACCUM0 Reading yields lane 0’s raw shift and mask value (BASE0 not added). Table 75. INTERP1_ACCUM0_AD D Register Bits Name Description Type Reset 31:24 Reserved. - - - 23:0 NONAME RW 0x000000 INTERP1_ACCUM1_ADD Register Description Values written here are atomically added to ACCUM1 Reading yields lane 1’s raw shift and mask value (BASE1 not added). Table 76.
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RP2040 Datasheet Table 79. SPINLOCK1 Register Bits Name Description Type Reset 31:0 NONAME Reading from a spinlock address will: RO 0x00000002 - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. SPINLOCK2 Register Table 80.
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RP2040 Datasheet Table 82. SPINLOCK4 Register Bits Name Description Type Reset 31:0 NONAME Reading from a spinlock address will: RO 0x00000010 - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. SPINLOCK5 Register Table 83.
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RP2040 Datasheet Table 85. SPINLOCK7 Register Bits Name Description Type Reset 31:0 NONAME Reading from a spinlock address will: RO 0x00000080 - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. SPINLOCK8 Register Table 86.
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RP2040 Datasheet Table 88. SPINLOCK10 Register Bits Name Description Type Reset 31:0 NONAME Reading from a spinlock address will: RO 0x00000400 - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. SPINLOCK11 Register Table 89.
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RP2040 Datasheet Table 91. SPINLOCK13 Register Bits Name Description Type Reset 31:0 NONAME Reading from a spinlock address will: RO 0x00002000 - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. SPINLOCK14 Register Table 92.
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RP2040 Datasheet Table 94. SPINLOCK16 Register Bits Name Description Type Reset 31:0 NONAME Reading from a spinlock address will: RO 0x00010000 - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. SPINLOCK17 Register Table 95.
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RP2040 Datasheet Table 97. SPINLOCK19 Register Bits Name Description Type Reset 31:0 NONAME Reading from a spinlock address will: RO 0x00080000 - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. SPINLOCK20 Register Table 98.
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RP2040 Datasheet Table 100. SPINLOCK22 Register Bits Name Description Type Reset 31:0 NONAME Reading from a spinlock address will: RO 0x00400000 - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. SPINLOCK23 Register Table 101.
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RP2040 Datasheet Table 103. SPINLOCK25 Register Bits Name Description Type Reset 31:0 NONAME Reading from a spinlock address will: RO 0x02000000 - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. SPINLOCK26 Register Table 104.
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RP2040 Datasheet Table 106. SPINLOCK28 Register Bits Name Description Type Reset 31:0 NONAME Reading from a spinlock address will: RO 0x10000000 - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. SPINLOCK29 Register Table 107.
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RP2040 Datasheet Table 109. SPINLOCK31 Register Bits Name Description Type Reset 31:0 NONAME Reading from a spinlock address will: RO 0x80000000 - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. 2.3.2.
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RP2040 Datasheet  NOTE the event flag is "sticky", so if both processors send an event (SEV) simultaneously, and then both go to sleep (WFE), they will both wake immediately, rather than getting stuck in a sleep state. While in a WFE (or WFI) sleep state, the processor can shut off its internal clock gates, consuming much less power.
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RP2040 Datasheet has locked up, for example if code has been programmed into flash which permanently halts the system clock: in such a case, the normal debugger can not communicate with the processors to return the system to a working state, so more drastic action is needed. A rescue is invoked by setting the CDBGPWRUPREQ bit in the Rescue DP’s CTRL/STAT register.
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RP2040 Datasheet 2.4.1.2.
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RP2040 Datasheet Figure 11. Cortex M0+ Cortex-M0+ subsystem Functional block diagram Clock PMU Reset HCLK FCLK DCLK AHB-Lite Master Cortex M0+ Core MPU Bus Interface NVIC Breakpoint and watchpoint unit Debugger interface Single cycle IO Port RESET CTRL Interrupts WIC DAP Serial Wire Debug 2.4.2.2. Features The M0+ features: • The ARMv6-M Thumb® instruction set. • Thumb-2 technology. • An ARMv6-M compliant 24-bit SysTick timer. • A 32-bit hardware multiplier.
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RP2040 Datasheet • Support for unlimited software breakpoints using BKPT instruction. • Non-intrusive access to core peripherals and zero-waitstate system slaves through a compact bus matrix. A debugger can access these devices, including memory, even when the processor is running. • Full access to core registers when the processor is halted. • CoreSight compliant debug access through a Debug Access Port (DAP) supporting Serial Wire debug connections. 2.4.2.4.1.
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RP2040 Datasheet • A processor clock containing the core and associated interfaces Control is limited to clock enable/disable. When enabled, all domains run at the same clock speed. The PMU also interfaces with the WIC, to ensure that power-down and wake-up behaviors are transparent to software and work with clocking and sleeping requirements. This includes SLEEP or DEEPSLEEP support as controlled in SCR register. 2.4.2.8.1.
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RP2040 Datasheet • Any WFE wakeup event, or the execution of an exception return instruction, sets the Event Register. • A WFE instruction clears the Event Register. • Software cannot read or write the value of the Event Register directly. The Send-Event instruction The Send-Event (SEV) instruction causes an event to be signaled to the other processor. The Send-Event instruction generates a wakeup event.
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RP2040 Datasheet • Debug reset • M0+ core reset • PMU reset After power up, both processors are released from reset (see details in Section 2.12.2). This releases reset to Debug, M0+ core and PMU. Once running, resets can be triggered from the Debugger, NVIC (using AIRCR.SYSRESETREQ), or the RP2040 Power On State Machine controller (see details in Power-On State Machine).
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RP2040 Datasheet Operation Description Assembler Cycles 8-bit immediate ADDS Rd, Rd, # 1 With carry ADCS Rd, Rd, Rm 1 Immediate to SP ADD SP, SP, # 1 Form address from SP ADD Rd, SP, # 1 Form address from PC ADR Rd, 1 Lo and Lo SUBS Rd, Rn, Rm 1 3-bit immediate SUBS Rd, Rn, # 1 8-bit immediate SUBS Rd, Rd, # 1 With carry SBCS Rd, Rd, Rm 1 Immediate from SP SUB SP, SP, # 1 Negate RSBS Rd, Rn, #0 1 Multiply Multiply MULS Rd, Rm, Rd
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RP2040 Datasheet Operation Store Push Pop Branch Extend Reverse State Hint 2.4.
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RP2040 Datasheet Operation Barriers Description Assembler Cycles Wait For Interrupt WFI 2f Yield YIELD 1f No operation NOP 1 Instruction synchronization ISB 3 Data memory DMB 3 Data synchronization DSB 3 Table Notes a 2 if to AHB interface or SCS, 1 if to single-cycle I/O port. b N is the number of elements in the list. c N is the number of elements in the list including PC or LR. d 2 if taken, 1 if not-taken. e Cycle count depends on processor and debug configuration.
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RP2040 Datasheet Address range Code Data Device 0x00000000 - 0x1fffffff Yes Yes No a . Space reserved for Cortex-M0+ NVIC and debug components. Note Regions not marked as suitable for code behave as eXecute-Never (XN) and generate a HardFault exception if code attempts to execute from this location. See the ARMv6-M Architecture Reference Manual for more information about the memory model. 2.4.3.5. Processor core registers summary Table 113 shows the processor core register set summary.
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RP2040 Datasheet The processor implementation can TO DO (NICK): what do we have ? ensure that a fixed number of cycles are required for the NVIC to detect an interrupt signal and the processor fetch the first instruction of the associated interrupt handler. If this is done, the highest priority interrupt is jitter-free. See the documentation supplied by the processor implementer for more information.
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RP2040 Datasheet 2.4.5. NVIC 2.4.5.1. About the NVIC External interrupt signals connect to the NVIC, and the NVIC prioritizes the interrupts. Software can set the priority of each interrupt. The NVIC and the Cortex-M0+ processor core are closely coupled, providing low latency interrupt processing and efficient processing of late arriving interrupts. All NVIC registers are only accessible using word transfers. Any attempt to read or write a halfword or byte individually is unpredictable.
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RP2040 Datasheet 2.4.6. MPU 2.4.6.1. About the MPU The MPU is a component for memory protection which allows the processor to support the ARMv6 Protected Memory System Architecture model. The MPU provides full support for: • Eight unified protection regions. • Overlapping protection regions, with ascending region priority: ◦ 7 = highest priority. ◦ 0 = lowest priority. • Access permissions. • Exporting memory attributes to the system. MPU mismatches and permission violations invoke the HardFault handler.
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RP2040 Datasheet 2.4.8. List of Registers Table 117.
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RP2040 Datasheet Table 118. SYST_CSR Register Bits Name Description Type Reset 31:17 Reserved. - - - 16 COUNTFLAG Returns 1 if timer counted to 0 since last time this was RO 0x0 read. Clears on read by application or debugger. 15:3 Reserved. - - - 2 CLKSOURCE SysTick clock source. Always reads as one if SYST_CALIB RW 0x0 RW 0x0 RW 0x0 reports NOREF. Selects the SysTick timer clock source: 0 = External reference clock. 1 = Processor clock.
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RP2040 Datasheet Table 120. SYST_CVR Register Bits Name Description Type Reset 31:24 Reserved. - - - 23:0 CURRENT Reads return the current value of the SysTick counter. This RW 0x000000 register is write-clear. Writing to it with any value clears the register to 0. Clearing this register also clears the COUNTFLAG bit of the SysTick Control and Status Register.
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RP2040 Datasheet Table 123. NVIC_ICER Register Bits Name Description Type Reset 31:0 CLRENA Interrupt clear-enable bits. RW 0x00000000 Write: 0 = No effect. 1 = Disable interrupt. Read: 0 = Interrupt disabled. 1 = Interrupt enabled. NVIC_ISPR Register Description The NVIC_ISPR forces interrupts into the pending state, and shows which interrupts are pending. Table 124. NVIC_ISPR Register Bits Name Description Type Reset 31:0 SETPEND Interrupt set-pending bits.
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RP2040 Datasheet Bits Name Description Type Reset 23:22 IP_2 Priority of interrupt 2 RW 0x0 21:16 Reserved. - - - 15:14 IP_1 Priority of interrupt 1 RW 0x0 13:8 Reserved. - - - 7:6 IP_0 Priority of interrupt 0 RW 0x0 5:0 Reserved. - - - NVIC_IPR1 Register Description Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. Table 127.
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RP2040 Datasheet Description Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. Table 129. NVIC_IPR3 Register Bits Name Description Type Reset 31:30 IP_15 Priority of interrupt 15 RW 0x0 29:24 Reserved. - - - 23:22 IP_14 Priority of interrupt 14 RW 0x0 21:16 Reserved. - - - 15:14 IP_13 Priority of interrupt 13 RW 0x0 13:8 Reserved.
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RP2040 Datasheet Bits Name Description Type Reset 7:6 IP_20 Priority of interrupt 20 RW 0x0 5:0 Reserved. - - - NVIC_IPR6 Register Description Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. Table 132. NVIC_IPR6 Register Bits Name Description Type Reset 31:30 IP_27 Priority of interrupt 27 RW 0x0 29:24 Reserved.
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RP2040 Datasheet Bits Name Description Type Reset 31:24 IMPLEMENTER Implementor code: 0x41 = ARM RO 0x41 23:20 VARIANT Major revision number n in the rnpm revision status: RO 0x0 RO 0xc 0x0 = Revision 0. 19:16 ARCHITECTURE Constant that defines the architecture of the processor: 0xC = ARMv6-M architecture. 15:4 PARTNO Number of processor within family: 0xC60 = Cortex-M0+ RO 0xc60 3:0 REVISION Minor revision number m in the rnpm revision status: RO 0x1 0x1 = Patch 1.
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RP2040 Datasheet Bits Name Description Type Reset 26 PENDSTSET SysTick exception set-pending bit. RW 0x0 RW 0x0 Write: 0 = No effect. 1 = Changes SysTick exception state to pending. Read: 0 = SysTick exception is not pending. 1 = SysTick exception is pending. 25 PENDSTCLR SysTick exception clear-pending bit. Write: 0 = No effect. 1 = Removes the pending state from the SysTick exception. This bit is WO. On a register read its value is Unknown. 24 Reserved.
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RP2040 Datasheet Bits Name Description Type Reset 31:16 VECTKEY Register key: RW 0x0000 RO 0x0 - - Reads as Unknown On writes, write 0x05FA to VECTKEY, otherwise the write is ignored. 15 ENDIANESS Data endianness implemented: 0 = Little-endian. 14:3 Reserved. - 2 SYSRESETREQ Writing 1 to this bit causes the SYSRESETREQ signal to the RW 0x0 outer system to be asserted to request a reset. The intention is to force a large system reset of all major components except for debug.
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RP2040 Datasheet Bits Name Description Type Reset 1 SLEEPONEXIT Indicates sleep-on-exit when returning from Handler mode RW 0x0 - - to Thread mode: 0 = Do not sleep when returning to Thread mode. 1 = Enter sleep, or deep sleep, on return from an ISR to Thread mode. Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application. 0 Reserved.
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RP2040 Datasheet Bits Name Description Type Reset 23:22 PRI_14 Priority of system handler 14, PendSV RW 0x0 21:0 Reserved. - - - SHCSR Register Description Use the System Handler Control and State Register to determine or clear the pending status of SVCall. Table 142. SHCSR Register Bits Name Description Type Reset 31:16 Reserved. - - - 15 SVCALLPENDED Reads as 1 if SVCall is Pending. Write 1 to set pending RW 0x0 - - SVCall, write 0 to clear pending SVCall. 14:0 Reserved.
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RP2040 Datasheet Bits Name Description Type Reset 2 PRIVDEFENA Controls whether the default memory map is enabled as a RW 0x0 RW 0x0 RW 0x0 background region for privileged accesses. This bit is ignored when ENABLE is clear. 0 = If the MPU is enabled, disables use of the default memory map. Any memory access to a location not covered by any enabled region causes a fault. 1 = If the MPU is enabled, enables use of the default memory map as a background region for privileged software accesses.
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RP2040 Datasheet Bits Name Description Type Reset 4 VALID On writes, indicates whether the write must update the RW 0x0 RW 0x0 base address of the region identified by the REGION field, updating the MPU_RNR to indicate this new region. Write: 0 = MPU_RNR not changed, and the processor: Updates the base address for the region specified in the MPU_RNR. Ignores the value of the REGION field. 1 = The processor: Updates the value of the MPU_RNR to the value of the REGION field.
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RP2040 Datasheet 2.5.1. ROM A 16kB read-only memory (ROM) is at address 0x00000000. The ROM contents are fixed at the time the silicon is manufactured. It contains: • Initial startup routine • Flash boot sequence • Flash programming routines • USB mass storage device with UF2 support • Utility libraries such as fast floating point The boot sequence of the chip is defined in Section 2.7.2, and the ROM contents is described in more detail in Bootrom.
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RP2040 Datasheet Software may choose to use these for per-core purposes, e.g. stack and frequently-executed code, guaranteeing that the processors never stall on these accesses. However, like all SRAM on RP2040, these banks have single-cycle access from all masters providing no other masters are accessing the bank in the same cycle, so it is reasonable to treat memory as a single 264kB device. The four 64kB banks are also available at a non-striped mirror.
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RP2040 Datasheet Figure 12. Flash execute-in-place (XIP) subsystem. System accesses via the main AHB-Lite slave are decoded to determine if they are XIP accesses, direct accesses to the SSI e.g. for configuration, or accesses to various other hardware and control registers in the XIP subsystem. XIP accesses are first looked up in the cache, to accelerate accesses to recentlyused data.
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RP2040 Datasheet 2.5.3.2. Cache Flushing and Maintenance The FLUSH register allows the entire cache contents to be flushed. This is necessary if software has reprogrammed the flash contents, and needs to clear out stale data and code, without performing a reboot.
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RP2040 Datasheet 2.5.3.4. Flash Streaming and Auxiliary Bus Slave As the flash is generally much larger than SRAM, it’s often useful to stream chunks of data into memory from flash. It’s convenient to have the DMA stream this data in the background while software in the foreground is doing other things, and it’s even more convenient if code can continue to execute from flash whilst this takes place.
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RP2040 Datasheet 2. The number of XIP accesses which resulted in a cache hit For common use cases, this allows the cache hit rate to be profiled. 2.5.3.6. List of XIP Registers Table 149.
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RP2040 Datasheet Bits Name Description Type Reset 0 EN When 1, enable the cache. When the cache is disabled, all RW 0x1 XIP accesses will go straight to the flash, without querying the cache. When enabled, cacheable XIP accesses will query the cache, and the flash will not be accessed if the tag matches and the valid bit is set. If the cache is enabled, cache-as-SRAM accesses have no effect on the cache data RAM, and will produce a bus error response.
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RP2040 Datasheet Table 153. CTR_HIT Register Bits Name Description Type Reset 31:0 NONAME A 32 bit saturating counter that increments upon each WC 0x00000000 cache hit, i.e. when an XIP access is serviced directly from cached data. Write any value to clear. CTR_ACC Register Description Cache Access counter Table 154.
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RP2040 Datasheet Table 156. STREAM_CTR Register Bits Name Description Type Reset 31:22 Reserved. - - - 21:0 NONAME Write a nonzero value to start a streaming read. This will RW 0x000000 then progress in the background, using flash idle cycles to transfer a linear data block from flash to the streaming FIFO. Decrements automatically (1 at a time) as the stream progresses, and halts on reaching 0.
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RP2040 Datasheet • Processor core 1 low power wait and launch protocol. • USB MSC class-compliant bootloader with UF2 support for downloading code/data to FLASH or RAM. • USB PICOBOOT bootloader interface for advanced management. • Routines for programming and manipulating the external flash. • Fast single-precision floating point library. • Fast bit counting / manipulation functions. • Fast memory fill / copy functions. 2.7.1. Bootrom Source The bootrom source can be found at https://github.
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RP2040 Datasheet ◦ The debug host (which initiated the rescue) will provide further instruction. • If watchdog scratch registers set to indicate pre-loaded code exists in SRAM, jump to that code • Check if SPI CS pin is tied low ("bootrom button"), and skip flash boot if so.
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RP2040 Datasheet After issuing the XIP exit sequence, the Bootrom attempts to read in the second stage from flash using standard 03h serial read commands, which are near-universally supported. Since the Bootrom is immutable, it aims for compatibility rather than performance. 2.7.2.3. Flash Second Stage The flash second stage must configure the SSI and the external flash for the best possible execute-in-place performance.
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RP2040 Datasheet 0x00000016 16 bit pointer Pointer to a public data lookup table (rom_data_table) 0x00000018 16 bit pointer Pointer to a helper function (rom_table_lookup()) 2.7.3.1. Bootrom Functions The Bootrom contains a number of public functions that provide useful RP2040 functionality that might be needed in the absence of any other code on the device, as well as highly optimized versions of certain key functionality that would otherwise have to take up space in most user binaries.
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RP2040 Datasheet Counting / Manipulation Functions. CODE 'P','3' Cycles Avg Cycles Avg Description V1 V2 18 20 uint32_t _popcount32(uint32_t value) Return a count of the number of 1 bits in value. 'R','3' 21 22 uint32_t _reverse32(uint32_t value) Return the bits of value in the reverse order. 'L','3' 13 9.6 uint32_t _clz32(uint32_t value) Return the number of consecutive high order 0 bits of value. If value is zero, returns 32.
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RP2040 Datasheet 'E','X' void _flash_exit_xip(void) First set up the SSI for serial-mode operations, then issue the fixed XIP exit sequence described in Section 2.7.2.2. Note that the bootrom code uses the IO forcing logic to drive the CS pin, which must be cleared before returning the SSI to XIP mode (e.g. by a call to _flash_flush_cache). This function configures the SSI with a fixed SCK clock divisor of /6.
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RP2040 Datasheet 'D','E' _debug_trampoline_end This is the address of the final BKPT #0 instruction of debug_trampoline. This can be compared with the program counter to detect completion of the debug_trampoline call. 2.7.3.1.5. Miscellaneous Functions These remaining functions don’t fit in other categories and are exposed in the Pico SDK via the pico_bootrom library (see pico_bootrom). Table 162.
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RP2040 Datasheet better. The scientific functions are calculated using internal fixed-point representations so accuracy (as measured in ULP error rather than in absolute terms) is poorer in situations where converting the result back to floating point entails a large normalising shift. This occurs, for example, when calculating the sine of a value near a multiple of pi, the cosine of a value near an odd multiple of pi/2, or the logarithm of a value near 1.
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RP2040 Datasheet 0x10 N/A N/A deprecated Do not use this function 0x14 N/A N/A deprecated Do not use this function 0x18 63 63 float _fsqrt(float v) Return 0x1c 37 40 or -Infinity if v is negative.
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RP2040 Datasheet 0x44 669 653 float _ftan(float angle) Return the tangent of angle. angle is in radians, and must be in the range -128 to 128 0x48 N/A N/A deprecated Do not use this function 0x4c 542 524 float _fexp(float v) Return the exponential value of v, i.e. so 0x50 810 789 float _fln( float v) Return the natural logarithm of v.
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RP2040 Datasheet 0x70 N/A 53 _float2fix64 Convert a float to a signed fixed point 64-bit integer representation where n specifies the position of the binary point in the resulting fixed point representation e.g. _float2fix(0.5f, 16) == 0x8000.
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RP2040 Datasheet Offset V2 Cycles Description (Avg) 0x20 74 int _double2fix(double v, int n) Convert a double to a signed fixed point integer representation where n specifies the position of the binary point in the resulting fixed point representation - e.g. _double2fix(0.5f, 16) == 0x8000.
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RP2040 Datasheet Offset V2 Cycles Description (Avg) 0x50 428 double _dln( double v) Return the natural logarithm of v.
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RP2040 Datasheet Offset V2 Cycles Description (Avg) 0x78 52 _double2ufix64 Convert a double to an unsigned fixed point 64-bit integer representation where n specifies the position of the binary point in the resulting fixed point representation, e.g. _double2ufix(0.5f, 16) == 0x8000. This method rounds towards -Infinity, and clamps the resulting integer to lie within the range 0x0000000000000000 to 0xFFFFFFFFFFFFFFFF 0x7c 23 float _double2float(double v) Converts a double to a float 2.7.3.3.
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RP2040 Datasheet 2.7.4.1. The RPI-RP2 Drive The RP2040 appears as a standard 128MB flash drive named RPI-RP2 formatted as a single partition with FAT16. There are only ever two actual files visible on the drive specified. • INFO_UF2.TXT - contains a string description of the UF2 bootloader and version. • INDEX.HTM - redirects to information about the RP2040 device.
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RP2040 Datasheet Note that after downloading a regular flash binary, a reset is performed after which the flash binary second stage (at address 0x10000000 - the start of flash) will be entered (if valid) via the bootrom. A downloaded RAM Only binary is entered by watchdog reset into the start of the binary, which is calculated as the lowest address of a downloaded block (with Main RAM considered lower than Flash Cache if both are present).
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RP2040 Datasheet Table 167. PICOBOOT Interface Descriptor Field Value bLength 9 bDescriptorType 4 bInterfaceNumber varies bAlternateSetting 0 bNumEndpoints 2 bInterfaceClass 0xff (vendor specific) bInterfaceSubClass 0 bInterfaceProtocol 0 iInterface 0 2.7.5.3. Identifying The Endpoints The PICOBOOT interface provides a single BULK OUT and a single BULK IN endpoint. These can be identified by their direction and type. You should not rely on endpoint numbers. 2.7.5.4.
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RP2040 Datasheet Table 169.
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RP2040 Datasheet 2.7.5.4.4. READ (0x84) Read a contiguous memory (Flash or RAM or ROM) range from the RP2040 Table 172. PICOBOOT Read memory command (Flash, RAM, ROM) structure Offset Name Value / Description 0x08 bCmdId 0x84 (READ) 0x09 bCmdSize 0x08 0x0c dTransferLength Must be the same as dSize 0x10 dAddr The address to read from. May be in Flash or RAM or ROM 0x14 dSize The number of bytes to read 2.7.5.4.5.
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RP2040 Datasheet Offset Name Value / Description 0x09 bCmdSize 0x00 0x0c dTransferLength 0x00000000 2.7.5.4.8. EXEC (0x08) Executes a function on the device. This function takes no arguments and returns no results, so it must communicate via RAM. Execution of this method will block any other commands as well as Mass Storage Interface UF2 writes, so should only be used in exclusive mode and with extreme care (and it should save and restore registers as per the ARM EABI).
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RP2040 Datasheet 2.7.5.5. Control Requests The following requests are sent to the interface via the default control pipe. 2.7.5.5.1. INTERFACE_RESET (0x41) The host sends this control request to reset the PICOBOOT interface. This command: • Clears the HALT condition (if set) on each of the bulk endpoints • Aborts any in-process PICOBOOT or Mass Storage transfer and any flash write (this method is the only way to kill a stuck flash transfer).
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RP2040 Datasheet Offset Name Description 0x04 dStatusCode OK (0) The command completed successfully (or is in still in progress) UNKNOWN_CMD (1) The ID of the command was not recognized INVALID_CMD_LENGTH (2) The length of the command request was incorrect INVALID_TRANSFER_LENGT The data transfer length was incorrect given the command H (3) INVALID_ADDRESS (4) The address specified was invalid for the command type; i.e.
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RP2040 Datasheet  CAUTION If the digital IO is powered at a nominal 1.8V, the IO input thresholds should be adjusted via the VOLTAGE_SELECT register. By default, the IO input thresholds are valid when the digital IO is powered at a nominal voltage between 2.5V and 3.3V. See Section 2.18, “GPIO” for details. Powering the IO at 1.8V with input thresholds set for a 2.5V to 3.3V supply is a safe operating mode, but will result in input thresholds that do not meet specification.
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RP2040 Datasheet  NOTE It is safe to supply ADC_IOVDD at a higher or lower voltage than IOVDD, e.g. to power the ADC at 3.3V, for optimum performance, while supporting 1.8V signal levels on the digital IO. But the voltage on the ADC analogue inputs must not exceed IOVDD, e.g. if IOVDD is powered at 1.8V, the voltage on the ADC inputs should be limited to 1.8V. Voltages greater than IOVDD will result in leakage currents through the ESD protection diodes. See Section 5.2.3, “Pin Specifications” for details.
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RP2040 Datasheet 2.8.7.2. External Core Supply The digital core (DVDD) can be powered directly from an external 1.1V supply, rather than from the on-chip regulator, as shown in Figure 15. This approach may make sense if a suitable external regulator is available elsewhere in the system, or for low power applications where an efficient switched-mode regulator could be used instead of the less efficient linear on-chip voltage regulator.
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RP2040 Datasheet Figure 16. supporting 1.8V IO while using USB and the ADC 2.8.7.4. Single 1.8V Supply If a functional USB PHY and optimum ADC performance are not required, RP2040 can be powered from a single supply of less than 3.3V. Figure 17 shows an example with a single 1.8V supply. In this example, the core supply (DVDD) is regulated from the 1.8V supply by the on-chip voltage regulator. Figure 17. powering the chip from a single 1.8V supply 2.9.
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RP2040 Datasheet the chip’s digital IO supply IOVDD, simplifying the overall power supply requirements. To allow the chip to start up, the voltage regulator is enabled by default and will power-on as soon as its input supply is available. Once the chip is out of reset, the regulator can be disabled, placed into a high impedance state, or have its output voltage adjusted, under software control. The output voltage can be set in the range 0.80V to 1.30V in 50mV steps, but is set to a nominal 1.
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RP2040 Datasheet 2.9.2.2. High Impedance Mode In High Impedance mode, the voltage regulator is disabled and its output pin (VREG_VOUT) is set to a high impedance state. In this mode, the regulator’s power consumption is minimised. This mode allows a load connected to VREG_VOUT to be powered from a power source other than the on-chip regulator.
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RP2040 Datasheet Table 182. List of VREG_AND_CHIP_RES ET registers Offset Name Info 0x0 VREG Voltage regulator control and status 0x4 BOD brown-out detection control 0x8 CHIP_RESET Chip reset control and status VREG Register Description Voltage regulator control and status Table 183. VREG Register Bits Name Description Type Reset 31:13 Reserved. - - - 12 ROK regulation status RO 0x0 0=not in regulation, 1=in regulation 11:8 Reserved.
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RP2040 Datasheet Bits Name Description Type Reset 7:4 VSEL threshold select RW 0x9 0000 - 0.473V 0001 - 0.516V 0010 - 0.559V 0011 - 0.602V 0100 - 0.645V 0101 - 0.688V 0110 - 0.731V 0111 - 0.774V 1000 - 0.817V 1001 - 0.860V (default) 1010 - 0.903V 1011 - 0.946V 1100 - 0.989V 1101 - 1.032V 1110 - 1.075V 1111 - 1.118V 3:1 Reserved. - - - 0 EN enable RW 0x1 0=not enabled, 1=enabled CHIP_RESET Register Description Chip reset control and status Table 185.
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RP2040 Datasheet 2.9.7. Detailed Specifications Table 186. Voltage Regulator Detailed Specifications Parameter Description Min Typ Max Units VVREG_IOVDD input supply 1.63 1.8 - 3.3 3.63 V voltage ΔVVREG_VOUT output voltage -3 +3 variation IMAX output current ILIMIT current limit 150 ROKTH.
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RP2040 Datasheet 2.10.2. SLEEP State RP2040 enters the SLEEP state when all of the following are true: • Both processors are asleep (e.g. in a WFE or WFI instruction) • The system DMA has no outstanding transfers on any channel RP2040 exits the SLEEP state when either processor is awoken by an interrupt. When in the SLEEP state, the top-level clock gates are masked by the SLEEP_ENx registers (
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RP2040 Datasheet  CAUTION Memories must not be accessed when powered down. Doing so can corrupt memory contents. When powering a memory back up, a 20 ns delay is required before accessing the memory again. The XIP cache (see Execute-In-Place) can also be powered down, with CTRL.POWER_DOWN. The XIP hardware will not generate cache accesses whilst the cache is powered down.
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RP2040 Datasheet 2.10.5.2. Dormant The hello_dormant example, https://github.com/raspberrypi/pico-examples/tree/pre_release/sleep/hello_dormant/ hello_dormant.c, demonstrates dormant mode.
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RP2040 Datasheet Figure 19. The chiplevel reset subsystem psm_restart rst_n_psm external result (RUN) VREG_IOVDD DVDD Supply Monitor initialise_por_n rst_n_dp Power-on Reset initialise_n _por_n DVDD bod_n enable Brown-out Detection 2.11.2. Power-on Reset The power-on reset block makes sure the chip starts up cleanly when power is first applied by holding it in reset until the digital core supply (DVDD) can reliably power the chip’s core logic.
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RP2040 Datasheet Table 187. Power-on Reset Parameters Parameter Description Min Typ Max Units DVDDTH.POR power-on reset 0.924 0.957 0.99 V 3 10 μs threshold tPOR.ASSERT power-on reset assertion delay 2.11.3. Brown-out Detection The brown-out detection block prevents unreliable operation by initiating a power-on reset cycle if the digital core supply (DVDD) drops below a safe operating level.
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RP2040 Datasheet Figure 23. Disabling and enabling brownout detection EN 1 0 1 tBOD.ENABLE detection inactive detection inactive detection active Detection is re-enabled if the BOD register is reset, as this sets the register’s EN field to one. Again, detection will become active after a delay equal to the brown-out detection enable delay (tBOD.ENABLE).
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RP2040 Datasheet Parameter Description tBOD.ASSERT brown-out Min Typ Max Units 3 10 μs 35 55 μs 20 30 μs detection assertion delay tBOD.ENABLE brown-out detection enable delay tBOD.PROG brown-out detection programming delay 2.11.4. Supply Monitor The power-on and brown-out reset blocks are powered by the on-chip voltage regulator’s input supply (VREG_IOVDD).
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RP2040 Datasheet either a power-on or brown-out initiated reset, a one in the HAD_RUN field indicates the chip was last reset by the RUN pin, and a one in the HAD_PSM_RESTART field indicates the chip has been reset via Rescue Debug Port. There should never be more than one field set to one. 2.11.8. List of Registers The chip-level reset subsystem shares a register address space with the on-chip voltage regulator. The registers for both subsystems are listed in Section 2.9.6.
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RP2040 Datasheet • Ring Oscillator is started. rst_done is asserted once the ripple counter has seen a sufficient number of clock edges to indicate the ring oscillator is stable • Crystal Oscillator reset is deasserted. The crystal oscillator is not started at this point, so rst_done is asserted instantly. • clk_ref and clk_sys clock generators are taken out of reset. In the initial configuration clk_ref is running from the ring oscillator with no divider. clk_sys is running from clk_ref.
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RP2040 Datasheet FRCE_ON Register Description Force block out of reset (i.e. power it on) Table 191. FRCE_ON Register Bits Name Description Type Reset 31:17 Reserved.
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RP2040 Datasheet Bits Name 8 Description Type Reset sram2 RW 0x0 7 sram1 RW 0x0 6 sram0 RW 0x0 5 rom RW 0x0 4 busfabric RW 0x0 3 resets RW 0x0 2 clocks RW 0x0 1 xosc RW 0x0 0 rosc RW 0x0 WDSEL Register Description Set to 1 if the watchdog should reset this Table 193. WDSEL Register Bits Name Description Type Reset 31:17 Reserved.
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RP2040 Datasheet Description Is the subsystem ready? Table 194. DONE Register Bits Name Description Type Reset 31:17 Reserved. - - - 16 proc1 RO 0x0 15 proc0 RO 0x0 14 sio RO 0x0 13 vreg_and_chip_res RO 0x0 et 12 xip RO 0x0 11 sram5 RO 0x0 10 sram4 RO 0x0 9 sram3 RO 0x0 8 sram2 RO 0x0 7 sram1 RO 0x0 6 sram0 RO 0x0 5 rom RO 0x0 4 busfabric RO 0x0 3 resets RO 0x0 2 clocks RO 0x0 1 xosc RO 0x0 0 rosc RO 0x0 2.13.
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RP2040 Datasheet 2.13.2. Programmer’s Model The Pico SDK defines a struct to represent the resets registers. Pico SDK: https://github.com/raspberrypi/pico-sdk/tree/pre_release/src/rp2040/hardware_structs/include/hardware/structs/resets.
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RP2040 Datasheet 35 static inline void uart_unreset(uart_inst_t *uart) { 36 invalid_params_if(UART, uart != uart0 && uart != uart1); 37 unreset_block_wait(uart_hw_index(uart) ? RESETS_RESET_UART1_BITS : RESETS_RESET_UART0_BITS); 38 } 2.13.3. Registers Table 195. List of RESETS registers Offset Name 0x0 RESET 0x4 WDSEL 0x8 RESET_DONE Info RESET Register Table 196. RESET Register Bits Name Description Type Reset 31:25 Reserved.
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RP2040 Datasheet Bits Name 1 0 Description Type Reset busctrl RW 0x1 adc RW 0x1 WDSEL Register Table 197. WDSEL Register Bits Name Description Type Reset 31:25 Reserved.
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RP2040 Datasheet Bits Name 23 Description Type Reset uart1 RO 0x0 22 uart0 RO 0x0 21 timer RO 0x0 20 tbman RO 0x0 19 sysinfo RO 0x0 18 syscfg RO 0x0 17 spi1 RO 0x0 16 spi0 RO 0x0 15 rtc RO 0x0 14 pwm RO 0x0 13 pll_usb RO 0x0 12 pll_sys RO 0x0 11 pio1 RO 0x0 10 pio0 RO 0x0 9 pads_qspi RO 0x0 8 pads_bank0 RO 0x0 7 jtag RO 0x0 6 io_qspi RO 0x0 5 io_bank0 RO 0x0 4 i2c1 RO 0x0 3 i2c0 RO 0x0 2 dma RO 0x0 1 busctrl RO
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RP2040 Datasheet Figure 26. Clocks overview For very low cost or low power applications where precise timing is not required, the chip can be run from the internal Ring Oscillator (ROSC). Alternatively the user can provide external clocks or construct simple relaxation oscillators using the GPIOs and appropriate external passive components. Where timing is more critical, the Crystal Oscillator (XOSC) can provide an accurate reference to the 2 on-chip PLLs to provide fast clocking at precise frequencies.
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RP2040 Datasheet and Temperature). The frequency is likely to be in the range 4-8MHz and is guaranteed to be in the range 1-12MHz. For low cost applications where frequency accuracy is unimportant, the chip can continue to run from the ROSC. If greater performance is required the frequency can be increased by programming the registers as described in Ring Oscillator.
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RP2040 Datasheet ROSC frequency and adjust it accordingly. The reference could be the on-chip XOSC which can be turned on periodically for this purpose. This may be useful in a very low power application where it is too costly to run the XOSC continuously and too costly to use the PLLs to achieve high frequencies. If a time reference is available then the user should clock the on-chip RTC from the ROSC and periodically compare it against the time reference, then adjust the ROSC frequency as necessary.
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RP2040 Datasheet 2.14.2.4. Relaxation Oscillators If the user wants to use external clocks to replace or supplement the other clock sources but does not have an appropriate clock available, then 1 or 2 relaxation oscillators can be constructed using external passive components. Simply send the clock source (GPIN0 or GPIN1) to one of the gpclk0-3 generators, invert it through the GPIO logic and connect back to the clock source input via an RC circuit. Figure 27.
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RP2040 Datasheet Figure 28. A generic clock generator 2.14.3.1. Multiplexers The first multiplexer is referred to as the auxiliary mux and is a conventional design whose output will glitch when changing the select control. Clock glitches are to be avoided at all costs because they may corrupt the logic running on that clock. The clock generator output therefore cannot be used during such changes.
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RP2040 Datasheet Figure 29. An example of fractional division. All dividers support on-the-fly divisor changes meaning the output clock will switch cleanly from one divisor to another. So the clock generator does not need to be stopped during clock divisor changes. It does this by synchronising the divisor change to the end of the clock cycle. Similarly, the enable is synchronised to the end of the clock cycle so will not generate glitches when the clock generator is enabled or disabled.
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RP2040 Datasheet clk_sys_clocks does not have a wake mode enable because disabling it would prevent the cores from accessing the clocks control registers. The gpclks do not have clock enables. 2.14.3.4.2. System Sleep Mode System sleep mode is entered automatically when both cores are in sleep and the DMA has no outstanding transactions. In system sleep mode, the clock enables described in the previous paragraphs are switched from the WAKE_EN registers to the SLEEP_EN registers.
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RP2040 Datasheet 2.14.5. Resus It is possible to write software that inadvertently stops clk_sys. This will normally cause an unrecoverable lock-up of the cores and the on-chip debugger, leaving the user unable to trace the problem. To mitigate against that, an automatic resuscitation circuit is provided which will switch clk_sys to a known good clock source if no edges are detected over a user-defined interval. The known good source is clk_ref which can be driven from the XOSC, ROSC or an external source.
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RP2040 Datasheet Pico SDK: https://github.com/raspberrypi/pico-sdk/tree/pre_release/src/rp2040/hardware_structs/include/hardware/structs/clocks.
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RP2040 Datasheet 80 : "+r" (delay_cyc) 81 ); 82 83 } } 84 85 // Set aux mux first, and then glitchless mux if this clock has one 86 hw_write_masked(&clock->ctrl, 87 (auxsrc << CLOCKS_CLK_SYS_CTRL_AUXSRC_LSB), 88 89 CLOCKS_CLK_SYS_CTRL_AUXSRC_BITS ); 90 91 if (has_glitchless_mux(clk_index)) { 92 hw_write_masked(&clock->ctrl, 93 src << CLOCKS_CLK_REF_CTRL_SRC_LSB, 94 CLOCKS_CLK_REF_CTRL_SRC_BITS 95 ); 96 while (!(clock->selected & (1u << src))) 97 98 tight_loop_contents(); } 99 10
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RP2040 Datasheet  WARNING It is assumed the source frequency the programmer provides is correct. If it is not then the frequency returned by clock_get_hz will be inaccurate. 2.14.6.2. Using the frequency counter To use the frequency counter, the programmer must: • Set the reference frequency: clk_ref • Set the mux position of the source they want to measure.
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RP2040 Datasheet  NOTE The frequency counter can also be used in a test mode. This allows the hardware to check if the frequency is within a minimum frequency and a maximum frequency, set in FC0_MIN_KHZ and FC0_MAX_KHZ. In this mode, the PASS bit in FC0_STATUS will be set when DONE is set if the frequency is within the specified range. Otherwise, either the FAST or SLOW bit will be set. If the programmer attempts to count a stopped clock, or the clock stops running then the DIED bit will be set.
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RP2040 Datasheet Offset Name Info 0x48 CLK_PERI_CTRL Clock control, can be changed on-the-fly (except for auxsrc) 0x50 CLK_PERI_SELECTED Indicates which src is currently selected (one-hot) 0x54 CLK_USB_CTRL Clock control, can be changed on-the-fly (except for auxsrc) 0x58 CLK_USB_DIV Clock divisor, can be changed on-the-fly 0x5c CLK_USB_SELECTED Indicates which src is currently selected (one-hot) 0x60 CLK_ADC_CTRL Clock control, can be changed on-the-fly (except for auxsrc) 0x64 CLK_A
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RP2040 Datasheet CLK_GPOUT0_CTRL Register Description Clock control, can be changed on-the-fly (except for auxsrc) Table 201. CLK_GPOUT0_CTRL Register Bits Name Description Type Reset 31:21 Reserved. - - - 20 NUDGE An edge on this signal shifts the phase of the output by 1 RW 0x0 cycle of the input clock This can be done at any time 19:18 Reserved.
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RP2040 Datasheet Description Indicates which src is currently selected (one-hot) Table 203. CLK_GPOUT0_SELECT ED Register Bits Name 31:0 NONAME Description Type Reset RO 0x00000001 CLK_GPOUT1_CTRL Register Description Clock control, can be changed on-the-fly (except for auxsrc) Table 204. CLK_GPOUT1_CTRL Register Bits Name Description Type Reset 31:21 Reserved.
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RP2040 Datasheet Table 205. CLK_GPOUT1_DIV Register Bits Name Description Type Reset 31:8 INT Integer component of the divisor, 0 -> divide by 2^16 RW 0x000001 7:0 FRAC Fractional component of the divisor RW 0x00 Type Reset RO 0x00000001 CLK_GPOUT1_SELECTED Register Description Indicates which src is currently selected (one-hot) Table 206.
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RP2040 Datasheet CLK_GPOUT2_DIV Register Description Clock divisor, can be changed on-the-fly Table 208. CLK_GPOUT2_DIV Register Bits Name Description Type Reset 31:8 INT Integer component of the divisor, 0 -> divide by 2^16 RW 0x000001 7:0 FRAC Fractional component of the divisor RW 0x00 Type Reset RO 0x00000001 CLK_GPOUT2_SELECTED Register Description Indicates which src is currently selected (one-hot) Table 209.
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RP2040 Datasheet Bits Name Description Type Reset 4:0 Reserved. - - - CLK_GPOUT3_DIV Register Description Clock divisor, can be changed on-the-fly Table 211. CLK_GPOUT3_DIV Register Bits Name Description Type Reset 31:8 INT Integer component of the divisor, 0 -> divide by 2^16 RW 0x000001 7:0 FRAC Fractional component of the divisor RW 0x00 Type Reset RO 0x00000001 CLK_GPOUT3_SELECTED Register Description Indicates which src is currently selected (one-hot) Table 212.
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RP2040 Datasheet CLK_REF_SELECTED Register Description Indicates which src is currently selected (one-hot) Table 215. CLK_REF_SELECTED Register Bits Name 31:0 NONAME Description Type Reset RO 0x00000001 CLK_SYS_CTRL Register Description Clock control, can be changed on-the-fly (except for auxsrc) Table 216. CLK_SYS_CTRL Register Bits Name Description Type Reset 31:8 Reserved.
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RP2040 Datasheet Table 219. CLK_PERI_CTRL Register Bits Name Description Type Reset 31:12 Reserved. - - - 11 ENABLE Starts and stops the clock generator cleanly RW 0x0 10 KILL Asynchronously kills the clock generator RW 0x0 9:8 Reserved.
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RP2040 Datasheet Bits Name Description Type Reset 7:5 AUXSRC Selects the auxiliary clock source, will glitch when RW 0x0 - - switching 0x0 -> clksrc_pll_usb 0x1 -> clksrc_pll_sys 0x2 -> rosc_clksrc_ph 0x3 -> xosc_clksrc 0x4 -> clksrc_gpin0 0x5 -> clksrc_gpin1 4:0 Reserved. - CLK_USB_DIV Register Description Clock divisor, can be changed on-the-fly Table 222. CLK_USB_DIV Register Bits Name Description Type Reset 31:10 Reserved.
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RP2040 Datasheet Bits Name Description Type Reset 9:8 Reserved. - - - 7:5 AUXSRC Selects the auxiliary clock source, will glitch when RW 0x0 - - switching 0x0 -> clksrc_pll_usb 0x1 -> clksrc_pll_sys 0x2 -> rosc_clksrc_ph 0x3 -> xosc_clksrc 0x4 -> clksrc_gpin0 0x5 -> clksrc_gpin1 4:0 Reserved. - CLK_ADC_DIV Register Description Clock divisor, can be changed on-the-fly Table 225. CLK_ADC_DIV Register Bits Name Description Type Reset 31:10 Reserved.
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RP2040 Datasheet Bits Name Description Type Reset 10 KILL Asynchronously kills the clock generator RW 0x0 9:8 Reserved. - - - 7:5 AUXSRC Selects the auxiliary clock source, will glitch when RW 0x0 - - switching 0x0 -> clksrc_pll_usb 0x1 -> clksrc_pll_sys 0x2 -> rosc_clksrc_ph 0x3 -> xosc_clksrc 0x4 -> clksrc_gpin0 0x5 -> clksrc_gpin1 4:0 Reserved. - CLK_RTC_DIV Register Description Clock divisor, can be changed on-the-fly Table 228.
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RP2040 Datasheet Table 231. CLK_SYS_RESUS_STA TUS Register Bits Name Description Type Reset 31:1 Reserved. - - - 0 RESUSSED Clock has been resuscitated, correct the error then send RO 0x0 ctrl_clear=1 FC0_REF_KHZ Register Description Reference clock frequency in kHz Table 232. FC0_REF_KHZ Register Bits Name Description Type Reset 31:20 Reserved. - - - 19:0 NONAME RW 0x00000 FC0_MIN_KHZ Register Description Minimum pass frequency in kHz. This is optional.
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RP2040 Datasheet Table 236. FC0_INTERVAL Register Bits Name Description Type Reset 31:4 Reserved. - - - 3:0 NONAME RW 0x8 FC0_SRC Register Description Clock sent to frequency counter, set to 0 when not required Writing to this register initiates the frequency count Table 237. FC0_SRC Register Bits Name Description Type Reset 31:8 Reserved.
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RP2040 Datasheet Bits Name Description Type Reset 7:5 Reserved. - - - 4 DONE Test complete RO 0x0 3:1 Reserved. - - - 0 PASS Test passed RO 0x0 FC0_RESULT Register Description Result of frequency measurement, only valid when status_done=1 Table 239. FC0_RESULT Register Bits Name Description Type Reset 31:30 Reserved. - - - 29:5 KHZ RO 0x0000000 4:0 FRAC RO 0x00 Type Reset WAKE_EN0 Register Description enable clock in wake mode Table 240. WAKE_EN0 Register 2.
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RP2040 Datasheet Bits Name 11 10 Description Type Reset clk_sys_pads RW 0x1 clk_sys_vreg_and_ RW 0x1 chip_reset 9 clk_sys_jtag RW 0x1 8 clk_sys_io RW 0x1 7 clk_sys_i2c1 RW 0x1 6 clk_sys_i2c0 RW 0x1 5 clk_sys_dma RW 0x1 4 clk_sys_busfabric RW 0x1 3 clk_sys_busctrl RW 0x1 2 clk_sys_adc RW 0x1 1 clk_adc_adc RW 0x1 0 clk_sys_clocks RW 0x1 WAKE_EN1 Register Description enable clock in wake mode Table 241.
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RP2040 Datasheet Description enable clock in sleep mode Table 242.
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RP2040 Datasheet Description enable clock in sleep mode Table 243. SLEEP_EN1 Register Bits Name Description Type Reset 31:15 Reserved.
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RP2040 Datasheet Bits Name 18 Description Type Reset clk_sys_resets RO 0x0 17 clk_sys_pwm RO 0x0 16 clk_sys_psm RO 0x0 15 clk_sys_pll_usb RO 0x0 14 clk_sys_pll_sys RO 0x0 13 clk_sys_pio1 RO 0x0 12 clk_sys_pio0 RO 0x0 11 clk_sys_pads RO 0x0 10 clk_sys_vreg_and_ RO 0x0 chip_reset 9 clk_sys_jtag RO 0x0 8 clk_sys_io RO 0x0 7 clk_sys_i2c1 RO 0x0 6 clk_sys_i2c0 RO 0x0 5 clk_sys_dma RO 0x0 4 clk_sys_busfabric RO 0x0 3 clk_sys_busctrl RO 0x0 2 c
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RP2040 Datasheet Bits Name 3 Description Type Reset clk_sys_sysinfo RO 0x0 2 clk_sys_syscfg RO 0x0 1 clk_sys_sram5 RO 0x0 0 clk_sys_sram4 RO 0x0 INTR Register Description Raw Interrupts Table 246. INTR Register Bits Name Description Type Reset 31:1 Reserved. - - - 0 CLK_SYS_RESUS RO 0x0 INTE Register Description Interrupt Enable Table 247. INTE Register Bits Name Description Type Reset 31:1 Reserved.
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RP2040 Datasheet 2.15.1. Overview The Crystal Oscillator (XOSC) uses an external crystal to produce an accurate reference clock. The RP2040 supports 115MHz crystals and the reference design uses a 12MHz crystal. The reference clock is distributed to the PLLs, which can be used to multiply the XOSC frequency (for example, to provide a 48MHz USB clock and a 133MHz system clock). The XOSC clock is also a clock source for the clock generators, so can be used directly if required.
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RP2040 Datasheet ROSC to stop the output clock.  NOTE the PLLs must be stopped before entering DORMANT mode Pico SDK: https://github.com/raspberrypi/pico-sdk/tree/pre_release/src/rp2_common/hardware_xosc/xosc.
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RP2040 Datasheet ① Adding 128 ensures the integer result is always rounded up 23 xosc_hw->startup = startup_delay; 24 25 // Set the enable bit now that we have set freq range and startup delay 26 hw_set_bits(&xosc_hw->ctrl, XOSC_CTRL_ENABLE_VALUE_ENABLE << XOSC_CTRL_ENABLE_LSB); 27 28 // Wait for XOSC to be stable 29 while(!(xosc_hw->status & XOSC_STATUS_STABLE_BITS)); 30 } 2.15.7. List of registers Table 250.
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RP2040 Datasheet Bits Name Description Type Reset 30:25 Reserved. - - - 24 BADWRITE An invalid value has been written to CTRL_ENABLE or WC 0x0 - - CTRL_FREQ_RANGE or DORMANT 23:13 Reserved. - 12 ENABLED Oscillator is enabled but not necessarily running and stable RO - 11:2 Reserved.
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RP2040 Datasheet Description Note that div2 may not be implemented on this chip Table 256. PADREFCLK Register Bits Name Description Type Reset 31:1 Reserved. - - - 0 SELECT The output will glitch if this is changed on-the-fly RW 0x0 0x0 -> XOSC 0x1 -> XOSC_DIV2 CLKSRC Register Description clksrc_ph is an optional phase shifted version of clksrc and may not be implemented on this chip Table 257. CLKSRC Register Bits Name Description Type Reset 31:6 Reserved.
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RP2040 Datasheet Table 258. COUNT Register Bits Name Description Type Reset 31:8 Reserved. - - - 7:0 NONAME RW 0x00 2.16. Ring Oscillator (ROSC) 2.16.1. Overview A Ring Oscillator is an on-chip oscillator that requires no external crystal. Instead, the output is generated from a series of inverters that are chained together to create a feedback loop.
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RP2040 Datasheet  WARNING If no IRQ is configured before going into dormant mode the ROSC will never restart. See Section 2.10.5.2 for a some examples of dormant mode. 2.16.4. Programmer’s Model TO DO: LIAM: Document ring osc code in the SDK 2.16.5. List of registers Table 259.
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RP2040 Datasheet Description freqa & freqb control the frequency by controlling the drive strength of each stage The drive strength of each stage is given by: ds_stage[n] = 1+dsn[0]+dsn[1]+dsn[2] To calculate the frequency to a first approximation: for range=0: freq = fbase0 * 4/4 * (8+ds_stage[0]+ds_stage[1]+ds_stage[2]+ds_stage[3]+ds_stage[4]+ds_stage[5]+ds_stage[6]+ds_stage[7])/8 for range=1: freq = fbase0 * 4/3 * (6+ds_stage[0]+ds_stage[1]+ds_stage[2]+ds_stage[3]+ds_stage[4]+ds_stage[5])/6 for
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RP2040 Datasheet Bits Name Description Type Reset 3 Reserved. - - - 2:0 DS4 Stage 4 drive strength RW 0x0 DORMANT Register Description Ring Oscillator Power control Table 263.
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RP2040 Datasheet Table 266. STATUS Register Bits Name Description Type Reset 31 STABLE Oscillator is running and stable RO 0x0 30:25 Reserved. - - - 24 BADWRITE An invalid value has been written to CTRL_ENABLE or WC 0x0 CTRL_FREQ_RANGE or FRFEQA or FREQB or DORMANT 23:17 Reserved. - - - 16 DIV_RUNNING post-divider is running RO - 15:13 Reserved. - - - 12 ENABLED Oscillator is enabled but not necessarily running and stable RO - 11:0 Reserved.
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RP2040 Datasheet Figure 33. On both PLLs, the FREF (reference) input is crystal oscillator’s XI input. The PLL LOCK Lock Detect connected to the FOUTVCO FREF FOUTPOSTDIV contains a VCO, which is locked to a constant ÷1-63 PFD VCO ÷1-7 ÷1-7 ratio of the reference clock via the feedback REFDIV 6'b FBDIV 12'b 3'b loop (phase-frequency detector and loop filter).
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RP2040 Datasheet 2.17.2.1. Jitter vs Power Consumption There are often several ways to get the desired output frequency, especially if you are willing to add some margin to the desired output frequency (124 MHz or 126 Mhz instead of 125 MHz). It is up to the programmer to decide whether they optimise for low power consumption or low jitter. The lower the jitter, the lower the variation in the period of the clock.
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RP2040 Datasheet consumption. Here a 48 MHz output is requested: $ ./vcocalc.py 48 Requested: 48.0 MHz Achieved: 48.0 MHz VCO: 1440 MHz PD1: 6 PD2: 5 Asking for a 48 MHz output with a lower VCO frequency, if possible: $ ./vcocalc.py -l 48 Requested: 48.0 MHz Achieved: 48.0 MHz VCO: 432 MHz PD1: 3 PD2: 3 For a 125 MHz system clock with a 12 MHz input, the minimum VCO frequency is quite high. $ ./vcocalc.py -l 125 Requested: 125.0 MHz Achieved: 125.
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RP2040 Datasheet The pll_init function in the Pico SDK, which we will examine below, asserts that all of these conditions are true before attempting to configure the PLL. The Pico SDK defines the PLL control registers as a struct. It then maps them into memory for each instance of the PLL. Pico SDK: https://github.com/raspberrypi/pico-sdk/tree/pre_release/src/rp2040/hardware_structs/include/hardware/structs/pll.
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RP2040 Datasheet 50 hw_clear_bits(&pll->pwr, power); 51 52 // Wait for PLL to lock 53 while (!(pll->cs & PLL_CS_LOCK_BITS)) tight_loop_contents(); 54 55 // Set up post dividers - div1 feeds into div2 so if div1 is 5 and div2 is 2 then you get a divide by 10 56 uint32_t pdiv = (post_div1 << PLL_PRIM_POSTDIV1_LSB) | 57 58 (post_div2 << PLL_PRIM_POSTDIV2_LSB); pll->prim = pdiv; 59 60 // Turn on post divider 61 hw_clear_bits(&pll->pwr, PLL_PWR_POSTDIVPD_BITS); Note the VCO is turned on first, f
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RP2040 Datasheet Description Controls the PLL power modes. Table 271. PWR Register Bits Name Description Type Reset 31:6 Reserved. - - - 5 VCOPD PLL VCO powerdown RW 0x1 To save power set high when PLL output not required or bypass=1. 4 Reserved. - - - 3 POSTDIVPD PLL post divider powerdown RW 0x1 RW 0x1 To save power set high when PLL output not required or bypass=1. 2 DSMPD PLL DSM powerdown Nothing is achieved by setting this low. 1 Reserved.
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RP2040 Datasheet 2.18.1. Overview RP2040 has 36 multi-functional General Purpose Input / Output (GPIO) pins, divided into two banks. In a typical use case, the pins in the QSPI bank (QSPI_SS, QSPI_SCLK and QSPI_SD0 to QSPI_SD3) are used to execute code from an external flash device, leaving the User bank (GPIO0 to GPIO29) for the programmer to use. All GPIOs support digital input and output, but GPIO26 to GPIO29 can also be used as inputs to the chip’s Analogue to Digital Converter (ADC).
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RP2040 Datasheet Figure 34. Logical structure of a GPIO. Each GPIO can be controlled by one of a number of peripherals, or by software control registers in the SIO. The function select (FSEL) selects which peripheral output is in control of the GPIO’s direction and output level, and/or which peripheral input can see this GPIO’s input level. These three signals (output level, output enable, input level) can also be inverted, or forced high or low, using the GPIO control registers. 2.18.2.
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RP2040 Datasheet Function 21 SPI0 CSn UART1 RX I2C0 SCL PWM2 B SIO PIO0 PIO1 CLOCK GPOUT0 USB OVCUR DET 22 SPI0 SCK UART1 CTS I2C1 SDA PWM3 A SIO PIO0 PIO1 CLOCK GPIN1 USB VBUS DET 23 SPI0 TX UART1 RTS I2C1 SCL PWM3 B SIO PIO0 PIO1 CLOCK GPOUT1 USB VBUS EN 24 SPI1 RX UART1 TX I2C0 SDA PWM4 A SIO PIO0 PIO1 CLOCK GPOUT2 USB OVCUR DET 25 SPI1 CSn UART1 RX I2C0 SCL PWM4 B SIO PIO0 PIO1 CLOCK GPOUT3 USB VBUS DET 26 SPI1 SCK UART1 CTS I2C1 SDA PWM5 A SIO P
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RP2040 Datasheet Function Table 277. GPIO QSPI Bank function descriptions QSPI SD2 XIP SD2 SIO QSPI SD3 XIP SD3 SIO Function Name Description XIP Connection to the synchronous serial interface (SSI) inside the flash execute in place (XIP) subsystem. This allows processors to execute code directly from an external SPI, Dual-SPI or Quad-SPI flash SIO Software control of GPIO, from the single-cycle IO (SIO) block.
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RP2040 Datasheet 2.18.4. Pads Each GPIO is connected to the off-chip world via a "pad". Pads are the electrical interface between the chip’s internal logic and external circuitry. They translate signal voltage levels, support higher currents and offer some protection against electrostatic discharge (ESD) events. Pad electrical behaviour can be adjusted to meet the requirements of the external circuitry.
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RP2040 Datasheet 2.18.5.1. Select an IO function An IO pin can perform many different functions and must be configured before use. For example, you may want it to be a UART_TX pin, or a PWM output. The Pico SDK provides gpio_set_function for this purpose. Many Pico SDK examples will call gpio_set_function at the beginning so that it can print to a UART. The Pico SDK starts by defining a structure to represent the registers of IO bank 0, the User IO bank.
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RP2040 Datasheet 119 _gpio_set_irq_enabled(gpio, events, enable, irq_ctrl_base); 120 } gpio_set_irq_enabled uses a lower level function _gpio_set_irq_enabled: Pico SDK: https://github.com/raspberrypi/pico-sdk/tree/pre_release/src/rp2_common/hardware_gpio/gpio.
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RP2040 Datasheet 34 35 static const char *gpio_irq_str[] = { 36 "LEVEL_LOW", 37 "LEVEL_HIGH", // 0x2 // 0x1 38 "EDGE_FALL", // 0x4 39 "EDGE_RISE" // 0x8 40 }; 41 42 void gpio_event_string(char *buf, uint32_t events) { 43 for (uint i = 0; i < 4; i++) { 44 uint mask = (1 << i); 45 if (events & mask) { 46 // Copy this event string into the user string 47 const char *event_str = gpio_irq_str[i]; 48 while (*event_str != '\0') { 49 *buf++ = *event_str++; 50 } 51 events &= ~mask; 52 5
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RP2040 Datasheet 2.18. GPIO Offset Name Info 0x038 GPIO7_STATUS GPIO status 0x03c GPIO7_CTRL GPIO control including function select and overrides. 0x040 GPIO8_STATUS GPIO status 0x044 GPIO8_CTRL GPIO control including function select and overrides. 0x048 GPIO9_STATUS GPIO status 0x04c GPIO9_CTRL GPIO control including function select and overrides. 0x050 GPIO10_STATUS GPIO status 0x054 GPIO10_CTRL GPIO control including function select and overrides.
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RP2040 Datasheet 2.18. GPIO Offset Name Info 0x0c8 GPIO25_STATUS GPIO status 0x0cc GPIO25_CTRL GPIO control including function select and overrides. 0x0d0 GPIO26_STATUS GPIO status 0x0d4 GPIO26_CTRL GPIO control including function select and overrides. 0x0d8 GPIO27_STATUS GPIO status 0x0dc GPIO27_CTRL GPIO control including function select and overrides. 0x0e0 GPIO28_STATUS GPIO status 0x0e4 GPIO28_CTRL GPIO control including function select and overrides.
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RP2040 Datasheet Offset Name Info 0x158 PROC1_INTS2 Interrupt status after masking & forcing for proc1 0x15c PROC1_INTS3 Interrupt status after masking & forcing for proc1 0x160 DORMANT_WAKE_INTE0 Interrupt Enable for dormant_wake 0x164 DORMANT_WAKE_INTE1 Interrupt Enable for dormant_wake 0x168 DORMANT_WAKE_INTE2 Interrupt Enable for dormant_wake 0x16c DORMANT_WAKE_INTE3 Interrupt Enable for dormant_wake 0x170 DORMANT_WAKE_INTF0 Interrupt Force for dormant_wake 0x174 DORMANT_WAKE_I
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RP2040 Datasheet GPIO0_CTRL, GPIO1_CTRL, …, GPIO28_CTRL, GPIO29_CTRL Registers Description GPIO control including function select and overrides. Table 280. GPIO0_CTRL, GPIO1_CTRL, …, GPIO28_CTRL, GPIO29_CTRL Registers Bits Name Description Type Reset 31:30 Reserved. - - - 29:28 IRQOVER 0x0 -> don’t invert the interrupt RW 0x0 0x1 -> invert the interrupt 0x2 -> drive interrupt low 0x3 -> drive interrupt high 27:18 Reserved.
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RP2040 Datasheet Table 281.
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RP2040 Datasheet Bits Name 10 GPIO2_EDGE_LO Description Type Reset WC 0x0 RO 0x0 RO 0x0 WC 0x0 WC 0x0 RO 0x0 RO 0x0 WC 0x0 WC 0x0 RO 0x0 RO 0x0 Type Reset WC 0x0 WC 0x0 RO 0x0 RO 0x0 WC 0x0 WC 0x0 RO 0x0 RO 0x0 W 9 GPIO2_LEVEL_HIG H 8 GPIO2_LEVEL_LO W 7 GPIO1_EDGE_HIG H 6 GPIO1_EDGE_LO W 5 GPIO1_LEVEL_HIG H 4 GPIO1_LEVEL_LO W 3 GPIO0_EDGE_HIG H 2 GPIO0_EDGE_LO W 1 GPIO0_LEVEL_HIG H 0 GPIO0_LEVEL_LO W INTR1 Register Description Raw Interrupt
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RP2040 Datasheet Bits Name 23 GPIO13_EDGE_HI Description Type Reset WC 0x0 WC 0x0 RO 0x0 RO 0x0 WC 0x0 WC 0x0 RO 0x0 RO 0x0 WC 0x0 WC 0x0 RO 0x0 RO 0x0 WC 0x0 WC 0x0 RO 0x0 RO 0x0 WC 0x0 WC 0x0 RO 0x0 RO 0x0 WC 0x0 GH 22 GPIO13_EDGE_LO W 21 GPIO13_LEVEL_HI GH 20 GPIO13_LEVEL_L OW 19 GPIO12_EDGE_HI GH 18 GPIO12_EDGE_LO W 17 GPIO12_LEVEL_HI GH 16 GPIO12_LEVEL_L OW 15 GPIO11_EDGE_HI GH 14 GPIO11_EDGE_LO W 13 GPIO11_LEVEL_HI GH 12 GPIO11_LEV
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RP2040 Datasheet Bits Name 2 GPIO8_EDGE_LO Description Type Reset WC 0x0 RO 0x0 RO 0x0 Type Reset WC 0x0 WC 0x0 RO 0x0 RO 0x0 WC 0x0 WC 0x0 RO 0x0 RO 0x0 WC 0x0 WC 0x0 RO 0x0 RO 0x0 WC 0x0 WC 0x0 RO 0x0 RO 0x0 W 1 GPIO8_LEVEL_HIG H 0 GPIO8_LEVEL_LO W INTR2 Register Description Raw Interrupts Table 283.
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RP2040 Datasheet Bits Name 15 GPIO19_EDGE_HI Description Type Reset WC 0x0 WC 0x0 RO 0x0 RO 0x0 WC 0x0 WC 0x0 RO 0x0 RO 0x0 WC 0x0 WC 0x0 RO 0x0 RO 0x0 WC 0x0 WC 0x0 RO 0x0 RO 0x0 GH 14 GPIO19_EDGE_LO W 13 GPIO19_LEVEL_HI GH 12 GPIO19_LEVEL_L OW 11 GPIO18_EDGE_HI GH 10 GPIO18_EDGE_LO W 9 GPIO18_LEVEL_HI GH 8 GPIO18_LEVEL_L OW 7 GPIO17_EDGE_HI GH 6 GPIO17_EDGE_LO W 5 GPIO17_LEVEL_HI GH 4 GPIO17_LEVEL_L OW 3 GPIO16_EDGE_HI GH 2 GPIO16_EDGE_LO W
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RP2040 Datasheet Bits Name 21 GPIO29_LEVEL_HI Description Type Reset RO 0x0 RO 0x0 WC 0x0 WC 0x0 RO 0x0 RO 0x0 WC 0x0 WC 0x0 RO 0x0 RO 0x0 WC 0x0 WC 0x0 RO 0x0 RO 0x0 WC 0x0 WC 0x0 RO 0x0 RO 0x0 WC 0x0 WC 0x0 RO 0x0 GH 20 GPIO29_LEVEL_L OW 19 GPIO28_EDGE_HI GH 18 GPIO28_EDGE_LO W 17 GPIO28_LEVEL_HI GH 16 GPIO28_LEVEL_L OW 15 GPIO27_EDGE_HI GH 14 GPIO27_EDGE_LO W 13 GPIO27_LEVEL_HI GH 12 GPIO27_LEVEL_L OW 11 GPIO26_EDGE_HI GH 10 GPIO26_ED
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RP2040 Datasheet Bits Name 0 GPIO24_LEVEL_L Description Type Reset RO 0x0 Type Reset RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 OW PROC0_INTE0 Register Description Interrupt Enable for proc0 Table 285.
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RP2040 Datasheet Bits Name 13 GPIO3_LEVEL_HIG Description Type Reset RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 Type Reset RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 H 12 GPIO3_LEVEL_LO W 11 GPIO2_EDGE_HIG H 10 GPIO2_EDGE_LO W 9 GPIO2_LEVEL_HIG H 8 GPIO2_LEVEL_LO W 7 GPIO1_EDGE_HIG H 6 GPIO1_EDGE_LO W 5 GPIO1_LEVEL_HIG H 4 GPIO1_LEVEL_LO W 3 GPIO0_EDGE_HIG H 2 GPIO0_EDGE_LO W 1 GPIO0_LEVEL_H
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RP2040 Datasheet Bits Name 26 GPIO14_EDGE_LO Description Type Reset RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 W 25 GPIO14_LEVEL_HI GH 24 GPIO14_LEVEL_L OW 23 GPIO13_EDGE_HI GH 22 GPIO13_EDGE_LO W 21 GPIO13_LEVEL_HI GH 20 GPIO13_LEVEL_L OW 19 GPIO12_EDGE_HI GH 18 GPIO12_EDGE_LO W 17 GPIO12_LEVEL_HI GH 16 GPIO12_LEVEL_L OW 15 GPIO11_EDG
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RP2040 Datasheet Bits Name 5 GPIO9_LEVEL_HIG Description Type Reset RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 Type Reset RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 H 4 GPIO9_LEVEL_LO W 3 GPIO8_EDGE_HIG H 2 GPIO8_EDGE_LO W 1 GPIO8_LEVEL_HIG H 0 GPIO8_LEVEL_LO W PROC0_INTE2 Register Description Interrupt Enable for proc0 Table 287.
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RP2040 Datasheet Bits Name 18 GPIO20_EDGE_LO Description Type Reset RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 W 17 GPIO20_LEVEL_HI GH 16 GPIO20_LEVEL_L OW 15 GPIO19_EDGE_HI GH 14 GPIO19_EDGE_LO W 13 GPIO19_LEVEL_HI GH 12 GPIO19_LEVEL_L OW 11 GPIO18_EDGE_HI GH 10 GPIO18_EDGE_LO W 9 GPIO18_LEVEL_HI GH 8 GPIO18_LEVEL_L OW 7 GPIO17_EDGE_HI GH 6 GPIO17_ED
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RP2040 Datasheet Table 288. PROC0_INTE3 Register Bits Name Description Type Reset 31:24 Reserved.
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RP2040 Datasheet Bits Name 2 GPIO24_EDGE_LO Description Type Reset RW 0x0 RW 0x0 RW 0x0 Type Reset RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 W 1 GPIO24_LEVEL_HI GH 0 GPIO24_LEVEL_L OW PROC0_INTF0 Register Description Interrupt Force for proc0 Table 289.
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RP2040 Datasheet Bits Name 15 GPIO3_EDGE_HIG Description Type Reset RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 Type Reset RW 0x0 RW 0x0 RW 0x0 H 14 GPIO3_EDGE_LO W 13 GPIO3_LEVEL_HIG H 12 GPIO3_LEVEL_LO W 11 GPIO2_EDGE_HIG H 10 GPIO2_EDGE_LO W 9 GPIO2_LEVEL_HIG H 8 GPIO2_LEVEL_LO W 7 GPIO1_EDGE_HIG H 6 GPIO1_EDGE_LO W 5 GPIO1_LEVEL_HIG H 4 GPIO1_LEVEL_LO W 3 GPIO0_EDGE_
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RP2040 Datasheet Bits Name 28 GPIO15_LEVEL_L Description Type Reset RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 OW 27 GPIO14_EDGE_HI GH 26 GPIO14_EDGE_LO W 25 GPIO14_LEVEL_HI GH 24 GPIO14_LEVEL_L OW 23 GPIO13_EDGE_HI GH 22 GPIO13_EDGE_LO W 21 GPIO13_LEVEL_HI GH 20 GPIO13_LEVEL_L OW 19 GPIO12_EDGE_HI GH 18 GPIO12_EDGE_LO W 17 GPIO12_LEVE
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RP2040 Datasheet Bits Name 7 GPIO9_EDGE_HIG Description Type Reset RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 Type Reset RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 H 6 GPIO9_EDGE_LO W 5 GPIO9_LEVEL_HIG H 4 GPIO9_LEVEL_LO W 3 GPIO8_EDGE_HIG H 2 GPIO8_EDGE_LO W 1 GPIO8_LEVEL_HIG H 0 GPIO8_LEVEL_LO W PROC0_INTF2 Register Description Interrupt Force for proc0 Table 291.
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RP2040 Datasheet Bits Name 20 GPIO21_LEVEL_L Description Type Reset RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 OW 19 GPIO20_EDGE_HI GH 18 GPIO20_EDGE_LO W 17 GPIO20_LEVEL_HI GH 16 GPIO20_LEVEL_L OW 15 GPIO19_EDGE_HI GH 14 GPIO19_EDGE_LO W 13 GPIO19_LEVEL_HI GH 12 GPIO19_LEVEL_L OW 11 GPIO18_EDGE_HI GH 10 GPIO18_EDGE_LO W 9 GPIO18_LEVEL
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RP2040 Datasheet PROC0_INTF3 Register Description Interrupt Force for proc0 Table 292. PROC0_INTF3 Register Bits Name Description Type Reset 31:24 Reserved.
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RP2040 Datasheet Bits Name 4 GPIO25_LEVEL_L Description Type Reset RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 Type Reset RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 OW 3 GPIO24_EDGE_HI GH 2 GPIO24_EDGE_LO W 1 GPIO24_LEVEL_HI GH 0 GPIO24_LEVEL_L OW PROC0_INTS0 Register Description Interrupt status after masking & forcing for proc0 Table 293.
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RP2040 Datasheet Bits Name 17 GPIO4_LEVEL_HIG Description Type Reset RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 Type Reset RO 0x0 H 16 GPIO4_LEVEL_LO W 15 GPIO3_EDGE_HIG H 14 GPIO3_EDGE_LO W 13 GPIO3_LEVEL_HIG H 12 GPIO3_LEVEL_LO W 11 GPIO2_EDGE_HIG H 10 GPIO2_EDGE_LO W 9 GPIO2_LEVEL_HIG H 8 GPIO2_LEVEL_LO W 7 GPIO1_EDGE_HIG H 6 GPIO1_EDGE_LO W 5 GPIO1_LEV
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RP2040 Datasheet Bits Name 30 GPIO15_EDGE_LO Description Type Reset RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 W 29 GPIO15_LEVEL_HI GH 28 GPIO15_LEVEL_L OW 27 GPIO14_EDGE_HI GH 26 GPIO14_EDGE_LO W 25 GPIO14_LEVEL_HI GH 24 GPIO14_LEVEL_L OW 23 GPIO13_EDGE_HI GH 22 GPIO13_EDGE_LO W 21 GPIO13_LEVEL_HI GH 20 GPIO13_LEVEL_L OW 19 GPIO12_EDG
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RP2040 Datasheet Bits Name 9 GPIO10_LEVEL_HI Description Type Reset RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 Type Reset RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 GH 8 GPIO10_LEVEL_L OW 7 GPIO9_EDGE_HIG H 6 GPIO9_EDGE_LO W 5 GPIO9_LEVEL_HIG H 4 GPIO9_LEVEL_LO W 3 GPIO8_EDGE_HIG H 2 GPIO8_EDGE_LO W 1 GPIO8_LEVEL_HIG H 0 GPIO8_LEVEL_LO W PROC0_INTS2 Register Description Interrupt status after mas
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RP2040 Datasheet Bits Name 22 GPIO21_EDGE_LO Description Type Reset RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 W 21 GPIO21_LEVEL_HI GH 20 GPIO21_LEVEL_L OW 19 GPIO20_EDGE_HI GH 18 GPIO20_EDGE_LO W 17 GPIO20_LEVEL_HI GH 16 GPIO20_LEVEL_L OW 15 GPIO19_EDGE_HI GH 14 GPIO19_EDGE_LO W 13 GPIO19_LEVEL_HI GH 12 GPIO19_LEVEL_L OW 11 GPIO18_EDG
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RP2040 Datasheet Bits Name 1 GPIO16_LEVEL_HI Description Type Reset RO 0x0 RO 0x0 GH 0 GPIO16_LEVEL_L OW PROC0_INTS3 Register Description Interrupt status after masking & forcing for proc0 Table 296. PROC0_INTS3 Register Bits Name Description Type Reset 31:24 Reserved.
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RP2040 Datasheet Bits Name 7 GPIO25_EDGE_HI Description Type Reset RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 Type Reset RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 GH 6 GPIO25_EDGE_LO W 5 GPIO25_LEVEL_HI GH 4 GPIO25_LEVEL_L OW 3 GPIO24_EDGE_HI GH 2 GPIO24_EDGE_LO W 1 GPIO24_LEVEL_HI GH 0 GPIO24_LEVEL_L OW PROC1_INTE0 Register Description Interrupt Enable for proc1 Table 297.
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RP2040 Datasheet Bits Name 20 GPIO5_LEVEL_LO Description Type Reset RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 W 19 GPIO4_EDGE_HIG H 18 GPIO4_EDGE_LO W 17 GPIO4_LEVEL_HIG H 16 GPIO4_LEVEL_LO W 15 GPIO3_EDGE_HIG H 14 GPIO3_EDGE_LO W 13 GPIO3_LEVEL_HIG H 12 GPIO3_LEVEL_LO W 11 GPIO2_EDGE_HIG H 10 GPIO2_EDGE_LO W 9 GPIO2_LEVEL_HIG H 8 G
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RP2040 Datasheet PROC1_INTE1 Register Description Interrupt Enable for proc1 Table 298.
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RP2040 Datasheet Bits Name 11 GPIO10_EDGE_HI Description Type Reset RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 Type Reset RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 GH 10 GPIO10_EDGE_LO W 9 GPIO10_LEVEL_HI GH 8 GPIO10_LEVEL_L OW 7 GPIO9_EDGE_HIG H 6 GPIO9_EDGE_LO W 5 GPIO9_LEVEL_HIG H 4 GPIO9_LEVEL_LO W 3 GPIO8_EDGE_HIG H 2 GPIO8_EDGE_LO W 1 GPIO8_LEVEL_HIG H 0 GPIO8_LEVEL_LO W PROC1_INTE2 Re
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RP2040 Datasheet Bits Name 24 GPIO22_LEVEL_L Description Type Reset RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 OW 23 GPIO21_EDGE_HI GH 22 GPIO21_EDGE_LO W 21 GPIO21_LEVEL_HI GH 20 GPIO21_LEVEL_L OW 19 GPIO20_EDGE_HI GH 18 GPIO20_EDGE_LO W 17 GPIO20_LEVEL_HI GH 16 GPIO20_LEVEL_L OW 15 GPIO19_EDGE_HI GH 14 GPIO19_EDGE_LO W 13 GPIO19_LEVE
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RP2040 Datasheet Bits Name 3 GPIO16_EDGE_HI Description Type Reset RW 0x0 RW 0x0 RW 0x0 RW 0x0 GH 2 GPIO16_EDGE_LO W 1 GPIO16_LEVEL_HI GH 0 GPIO16_LEVEL_L OW PROC1_INTE3 Register Description Interrupt Enable for proc1 Table 300. PROC1_INTE3 Register Bits Name Description Type Reset 31:24 Reserved.
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RP2040 Datasheet Bits Name 9 GPIO26_LEVEL_HI Description Type Reset RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 Type Reset RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 GH 8 GPIO26_LEVEL_L OW 7 GPIO25_EDGE_HI GH 6 GPIO25_EDGE_LO W 5 GPIO25_LEVEL_HI GH 4 GPIO25_LEVEL_L OW 3 GPIO24_EDGE_HI GH 2 GPIO24_EDGE_LO W 1 GPIO24_LEVEL_HI GH 0 GPIO24_LEVEL_L OW PROC1_INTF0 Register Description Interrupt Force fo
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RP2040 Datasheet Bits Name 22 GPIO5_EDGE_LO Description Type Reset RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 W 21 GPIO5_LEVEL_HIG H 20 GPIO5_LEVEL_LO W 19 GPIO4_EDGE_HIG H 18 GPIO4_EDGE_LO W 17 GPIO4_LEVEL_HIG H 16 GPIO4_LEVEL_LO W 15 GPIO3_EDGE_HIG H 14 GPIO3_EDGE_LO W 13 GPIO3_LEVEL_HIG H 12 GPIO3_LEVEL_LO W 11 GPIO2_EDGE_HIG H 10
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RP2040 Datasheet Bits Name 1 GPIO0_LEVEL_HIG Description Type Reset RW 0x0 RW 0x0 Type Reset RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 H 0 GPIO0_LEVEL_LO W PROC1_INTF1 Register Description Interrupt Force for proc1 Table 302.
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RP2040 Datasheet Bits Name 14 GPIO11_EDGE_LO Description Type Reset RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 Type Reset RW 0x0 RW 0x0 RW 0x0 RW 0x0 W 13 GPIO11_LEVEL_HI GH 12 GPIO11_LEVEL_L OW 11 GPIO10_EDGE_HI GH 10 GPIO10_EDGE_LO W 9 GPIO10_LEVEL_HI GH 8 GPIO10_LEVEL_L OW 7 GPIO9_EDGE_HIG H 6 GPIO9_EDGE_LO W 5 GPIO9_LEVEL_HIG H 4 GPIO9_LEVEL_LO W 3 GPIO8_EDGE_HIG H 2 GPIO8
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RP2040 Datasheet Bits Name 27 GPIO22_EDGE_HI Description Type Reset RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 GH 26 GPIO22_EDGE_LO W 25 GPIO22_LEVEL_HI GH 24 GPIO22_LEVEL_L OW 23 GPIO21_EDGE_HI GH 22 GPIO21_EDGE_LO W 21 GPIO21_LEVEL_HI GH 20 GPIO21_LEVEL_L OW 19 GPIO20_EDGE_HI GH 18 GPIO20_EDGE_LO W 17 GPIO20_LEVEL_HI GH 16 GPIO20_LEV
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RP2040 Datasheet Bits Name 6 GPIO17_EDGE_LO Description Type Reset RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 W 5 GPIO17_LEVEL_HI GH 4 GPIO17_LEVEL_L OW 3 GPIO16_EDGE_HI GH 2 GPIO16_EDGE_LO W 1 GPIO16_LEVEL_HI GH 0 GPIO16_LEVEL_L OW PROC1_INTF3 Register Description Interrupt Force for proc1 Table 304. PROC1_INTF3 Register Bits Name Description Type Reset 31:24 Reserved.
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RP2040 Datasheet Bits Name 12 GPIO27_LEVEL_L Description Type Reset RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 Type Reset RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 OW 11 GPIO26_EDGE_HI GH 10 GPIO26_EDGE_LO W 9 GPIO26_LEVEL_HI GH 8 GPIO26_LEVEL_L OW 7 GPIO25_EDGE_HI GH 6 GPIO25_EDGE_LO W 5 GPIO25_LEVEL_HI GH 4 GPIO25_LEVEL_L OW 3 GPIO24_EDGE_HI GH 2 GPIO24_EDGE_LO W 1 GPIO24_LEVEL_HI GH 0 GP
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RP2040 Datasheet Bits Name 25 GPIO6_LEVEL_HIG Description Type Reset RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 H 24 GPIO6_LEVEL_LO W 23 GPIO5_EDGE_HIG H 22 GPIO5_EDGE_LO W 21 GPIO5_LEVEL_HIG H 20 GPIO5_LEVEL_LO W 19 GPIO4_EDGE_HIG H 18 GPIO4_EDGE_LO W 17 GPIO4_LEVEL_HIG H 16 GPIO4_LEVEL_LO W 15 GPIO3_EDGE_HIG H 14 GPIO3_EDGE_LO W 13
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RP2040 Datasheet Bits Name 4 GPIO1_LEVEL_LO Description Type Reset RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 Type Reset RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 W 3 GPIO0_EDGE_HIG H 2 GPIO0_EDGE_LO W 1 GPIO0_LEVEL_HIG H 0 GPIO0_LEVEL_LO W PROC1_INTS1 Register Description Interrupt status after masking & forcing for proc1 Table 306.
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RP2040 Datasheet Bits Name 17 GPIO12_LEVEL_HI Description Type Reset RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 Type Reset RO 0x0 GH 16 GPIO12_LEVEL_L OW 15 GPIO11_EDGE_HI GH 14 GPIO11_EDGE_LO W 13 GPIO11_LEVEL_HI GH 12 GPIO11_LEVEL_L OW 11 GPIO10_EDGE_HI GH 10 GPIO10_EDGE_LO W 9 GPIO10_LEVEL_HI GH 8 GPIO10_LEVEL_L OW 7 GPIO9_EDGE_HIG H 6 GPIO9_EDGE_LO W 5
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RP2040 Datasheet Bits Name 30 GPIO23_EDGE_LO Description Type Reset RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 W 29 GPIO23_LEVEL_HI GH 28 GPIO23_LEVEL_L OW 27 GPIO22_EDGE_HI GH 26 GPIO22_EDGE_LO W 25 GPIO22_LEVEL_HI GH 24 GPIO22_LEVEL_L OW 23 GPIO21_EDGE_HI GH 22 GPIO21_EDGE_LO W 21 GPIO21_LEVEL_HI GH 20 GPIO21_LEVEL_L OW 19 GPIO20_EDG
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RP2040 Datasheet Bits Name 9 GPIO18_LEVEL_HI Description Type Reset RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 GH 8 GPIO18_LEVEL_L OW 7 GPIO17_EDGE_HI GH 6 GPIO17_EDGE_LO W 5 GPIO17_LEVEL_HI GH 4 GPIO17_LEVEL_L OW 3 GPIO16_EDGE_HI GH 2 GPIO16_EDGE_LO W 1 GPIO16_LEVEL_HI GH 0 GPIO16_LEVEL_L OW PROC1_INTS3 Register Description Interrupt status after masking & forcing for proc1 Table 308.
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RP2040 Datasheet Bits Name 15 GPIO27_EDGE_HI Description Type Reset RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 Type Reset RW 0x0 RW 0x0 RW 0x0 GH 14 GPIO27_EDGE_LO W 13 GPIO27_LEVEL_HI GH 12 GPIO27_LEVEL_L OW 11 GPIO26_EDGE_HI GH 10 GPIO26_EDGE_LO W 9 GPIO26_LEVEL_HI GH 8 GPIO26_LEVEL_L OW 7 GPIO25_EDGE_HI GH 6 GPIO25_EDGE_LO W 5 GPIO25_LEVEL_HI GH 4 GPIO25_LEVEL_L OW 3
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RP2040 Datasheet Bits Name 28 GPIO7_LEVEL_LO Description Type Reset RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 W 27 GPIO6_EDGE_HIG H 26 GPIO6_EDGE_LO W 25 GPIO6_LEVEL_HIG H 24 GPIO6_LEVEL_LO W 23 GPIO5_EDGE_HIG H 22 GPIO5_EDGE_LO W 21 GPIO5_LEVEL_HIG H 20 GPIO5_LEVEL_LO W 19 GPIO4_EDGE_HIG H 18 GPIO4_EDGE_LO W 17 GPIO4_LEVEL_HIG H 16
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RP2040 Datasheet Bits Name 7 GPIO1_EDGE_HIG Description Type Reset RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 Type Reset RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 H 6 GPIO1_EDGE_LO W 5 GPIO1_LEVEL_HIG H 4 GPIO1_LEVEL_LO W 3 GPIO0_EDGE_HIG H 2 GPIO0_EDGE_LO W 1 GPIO0_LEVEL_HIG H 0 GPIO0_LEVEL_LO W DORMANT_WAKE_INTE1 Register Description Interrupt Enable for dormant_wake Table 310.
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RP2040 Datasheet Bits Name 20 GPIO13_LEVEL_L Description Type Reset RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 OW 19 GPIO12_EDGE_HI GH 18 GPIO12_EDGE_LO W 17 GPIO12_LEVEL_HI GH 16 GPIO12_LEVEL_L OW 15 GPIO11_EDGE_HI GH 14 GPIO11_EDGE_LO W 13 GPIO11_LEVEL_HI GH 12 GPIO11_LEVEL_L OW 11 GPIO10_EDGE_HI GH 10 GPIO10_EDGE_LO W 9 GPIO10_LEVEL
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RP2040 Datasheet DORMANT_WAKE_INTE2 Register Description Interrupt Enable for dormant_wake Table 311.
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RP2040 Datasheet Bits Name 11 GPIO18_EDGE_HI Description Type Reset RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 GH 10 GPIO18_EDGE_LO W 9 GPIO18_LEVEL_HI GH 8 GPIO18_LEVEL_L OW 7 GPIO17_EDGE_HI GH 6 GPIO17_EDGE_LO W 5 GPIO17_LEVEL_HI GH 4 GPIO17_LEVEL_L OW 3 GPIO16_EDGE_HI GH 2 GPIO16_EDGE_LO W 1 GPIO16_LEVEL_HI GH 0 GPIO16_LEVEL_L OW DORMANT_WAKE_INTE3 Register Description Interrupt Enable for dormant_wake Table 31
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RP2040 Datasheet Bits Name 17 GPIO28_LEVEL_HI Description Type Reset RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 Type Reset RW 0x0 GH 16 GPIO28_LEVEL_L OW 15 GPIO27_EDGE_HI GH 14 GPIO27_EDGE_LO W 13 GPIO27_LEVEL_HI GH 12 GPIO27_LEVEL_L OW 11 GPIO26_EDGE_HI GH 10 GPIO26_EDGE_LO W 9 GPIO26_LEVEL_HI GH 8 GPIO26_LEVEL_L OW 7 GPIO25_EDGE_HI GH 6 GPIO25_EDGE_LO W
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RP2040 Datasheet Bits Name 30 GPIO7_EDGE_LO Description Type Reset RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 W 29 GPIO7_LEVEL_HIG H 28 GPIO7_LEVEL_LO W 27 GPIO6_EDGE_HIG H 26 GPIO6_EDGE_LO W 25 GPIO6_LEVEL_HIG H 24 GPIO6_LEVEL_LO W 23 GPIO5_EDGE_HIG H 22 GPIO5_EDGE_LO W 21 GPIO5_LEVEL_HIG H 20 GPIO5_LEVEL_LO W 19 GPIO4_EDGE_HIG H 18
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RP2040 Datasheet Bits Name 9 GPIO2_LEVEL_HIG Description Type Reset RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 Type Reset RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 H 8 GPIO2_LEVEL_LO W 7 GPIO1_EDGE_HIG H 6 GPIO1_EDGE_LO W 5 GPIO1_LEVEL_HIG H 4 GPIO1_LEVEL_LO W 3 GPIO0_EDGE_HIG H 2 GPIO0_EDGE_LO W 1 GPIO0_LEVEL_HIG H 0 GPIO0_LEVEL_LO W DORMANT_WAKE_INTF1 Register Description Interrupt Force for d
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RP2040 Datasheet Bits Name 22 GPIO13_EDGE_LO Description Type Reset RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 W 21 GPIO13_LEVEL_HI GH 20 GPIO13_LEVEL_L OW 19 GPIO12_EDGE_HI GH 18 GPIO12_EDGE_LO W 17 GPIO12_LEVEL_HI GH 16 GPIO12_LEVEL_L OW 15 GPIO11_EDGE_HI GH 14 GPIO11_EDGE_LO W 13 GPIO11_LEVEL_HI GH 12 GPIO11_LEVEL_L OW 11 GPIO10_EDG
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RP2040 Datasheet Bits Name 1 GPIO8_LEVEL_HIG Description Type Reset RW 0x0 RW 0x0 Type Reset RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 H 0 GPIO8_LEVEL_LO W DORMANT_WAKE_INTF2 Register Description Interrupt Force for dormant_wake Table 315.
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RP2040 Datasheet Bits Name 14 GPIO19_EDGE_LO Description Type Reset RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 W 13 GPIO19_LEVEL_HI GH 12 GPIO19_LEVEL_L OW 11 GPIO18_EDGE_HI GH 10 GPIO18_EDGE_LO W 9 GPIO18_LEVEL_HI GH 8 GPIO18_LEVEL_L OW 7 GPIO17_EDGE_HI GH 6 GPIO17_EDGE_LO W 5 GPIO17_LEVEL_HI GH 4 GPIO17_LEVEL_L OW 3 GPIO16_EDGE_HI GH 2 GPIO16_EDGE_LO W 1 GPIO16_LEVEL_HI GH 0 GPIO1
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RP2040 Datasheet Bits Name 20 GPIO29_LEVEL_L Description Type Reset RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 OW 19 GPIO28_EDGE_HI GH 18 GPIO28_EDGE_LO W 17 GPIO28_LEVEL_HI GH 16 GPIO28_LEVEL_L OW 15 GPIO27_EDGE_HI GH 14 GPIO27_EDGE_LO W 13 GPIO27_LEVEL_HI GH 12 GPIO27_LEVEL_L OW 11 GPIO26_EDGE_HI GH 10 GPIO26_EDGE_LO W 9 GPIO26_LEVEL
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RP2040 Datasheet DORMANT_WAKE_INTS0 Register Description Interrupt status after masking & forcing for dormant_wake Table 317.
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RP2040 Datasheet Bits Name 11 GPIO2_EDGE_HIG Description Type Reset RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 Type Reset RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 H 10 GPIO2_EDGE_LO W 9 GPIO2_LEVEL_HIG H 8 GPIO2_LEVEL_LO W 7 GPIO1_EDGE_HIG H 6 GPIO1_EDGE_LO W 5 GPIO1_LEVEL_HIG H 4 GPIO1_LEVEL_LO W 3 GPIO0_EDGE_HIG H 2 GPIO0_EDGE_LO W 1 GPIO0_LEVEL_HIG H 0 GPIO0_LEVEL_LO W DORMANT_WAKE_INTS1
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RP2040 Datasheet Bits Name 24 GPIO14_LEVEL_L Description Type Reset RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 OW 23 GPIO13_EDGE_HI GH 22 GPIO13_EDGE_LO W 21 GPIO13_LEVEL_HI GH 20 GPIO13_LEVEL_L OW 19 GPIO12_EDGE_HI GH 18 GPIO12_EDGE_LO W 17 GPIO12_LEVEL_HI GH 16 GPIO12_LEVEL_L OW 15 GPIO11_EDGE_HI GH 14 GPIO11_EDGE_LO W 13 GPIO11_LEVE
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RP2040 Datasheet Bits Name 3 GPIO8_EDGE_HIG Description Type Reset RO 0x0 RO 0x0 RO 0x0 RO 0x0 Type Reset RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 H 2 GPIO8_EDGE_LO W 1 GPIO8_LEVEL_HIG H 0 GPIO8_LEVEL_LO W DORMANT_WAKE_INTS2 Register Description Interrupt status after masking & forcing for dormant_wake Table 319.
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RP2040 Datasheet Bits Name 16 GPIO20_LEVEL_L Description Type Reset RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 OW 15 GPIO19_EDGE_HI GH 14 GPIO19_EDGE_LO W 13 GPIO19_LEVEL_HI GH 12 GPIO19_LEVEL_L OW 11 GPIO18_EDGE_HI GH 10 GPIO18_EDGE_LO W 9 GPIO18_LEVEL_HI GH 8 GPIO18_LEVEL_L OW 7 GPIO17_EDGE_HI GH 6 GPIO17_EDGE_LO W 5 GPIO17_LEVEL_HI GH 4 GPIO17_LEVEL_L OW 3 GPIO16_
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RP2040 Datasheet Bits Name 22 GPIO29_EDGE_LO Description Type Reset RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 W 21 GPIO29_LEVEL_HI GH 20 GPIO29_LEVEL_L OW 19 GPIO28_EDGE_HI GH 18 GPIO28_EDGE_LO W 17 GPIO28_LEVEL_HI GH 16 GPIO28_LEVEL_L OW 15 GPIO27_EDGE_HI GH 14 GPIO27_EDGE_LO W 13 GPIO27_LEVEL_HI GH 12 GPIO27_LEVEL_L OW 11 GPIO26_EDG
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RP2040 Datasheet Bits Name 1 GPIO24_LEVEL_HI Description Type Reset RO 0x0 RO 0x0 GH 0 GPIO24_LEVEL_L OW 2.18.6.2. IO - QSPI Bank Table 321. List of IO_QSPI registers Offset Name Info 0x00 GPIO_QSPI_SCLK_STATUS GPIO status 0x04 GPIO_QSPI_SCLK_CTRL GPIO control including function select and overrides. 0x08 GPIO_QSPI_SS_STATUS GPIO status 0x0c GPIO_QSPI_SS_CTRL GPIO control including function select and overrides.
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RP2040 Datasheet GPIO_QSPI_SD2_STAT US, GPIO_QSPI_SD3_STAT US Registers 2.18. GPIO Bits Name Description Type Reset 31:27 Reserved.
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RP2040 Datasheet Bits Name Description Type Reset 26 IRQTOPROC interrupt to processors, after override is applied RO 0x0 25 Reserved. - - - 24 IRQFROMPAD interrupt from pad before override is applied RO 0x0 23:20 Reserved. - - - 19 INTOPERI input signal to peripheral, after override is applied RO 0x0 18 Reserved. - - - 17 INFROMPAD input signal from pad, before override is applied RO 0x0 16:14 Reserved.
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RP2040 Datasheet Bits Name Description Type Reset 9:8 OUTOVER 0x0 -> drive output from peripheral signal selected by RW 0x0 funcsel 0x1 -> drive output from inverse of peripheral signal selected by funcsel 0x2 -> drive output low 0x3 -> drive output high 7:5 Reserved. - - - 4:0 FUNCSEL 0-31 -> selects pin function according to the gpio table RW 0x1f 31 == NULL 0x00 -> xip_sclk 0x05 -> sio_30 0x1f -> null INTR Register Description Raw Interrupts Table 324.
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RP2040 Datasheet Bits Name 10 GPIO_QSPI_SD0_E Description Type Reset WC 0x0 RO 0x0 RO 0x0 WC 0x0 WC 0x0 RO 0x0 RO 0x0 WC 0x0 WC 0x0 RO 0x0 RO 0x0 DGE_LOW 9 GPIO_QSPI_SD0_L EVEL_HIGH 8 GPIO_QSPI_SD0_L EVEL_LOW 7 GPIO_QSPI_SS_ED GE_HIGH 6 GPIO_QSPI_SS_ED GE_LOW 5 GPIO_QSPI_SS_LE VEL_HIGH 4 GPIO_QSPI_SS_LE VEL_LOW 3 GPIO_QSPI_SCLK_ EDGE_HIGH 2 GPIO_QSPI_SCLK_ EDGE_LOW 1 GPIO_QSPI_SCLK_ LEVEL_HIGH 0 GPIO_QSPI_SCLK_ LEVEL_LOW PROC0_INTE Register Description Inter
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RP2040 Datasheet Bits Name 16 GPIO_QSPI_SD2_L Description Type Reset RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 EVEL_LOW 15 GPIO_QSPI_SD1_E DGE_HIGH 14 GPIO_QSPI_SD1_E DGE_LOW 13 GPIO_QSPI_SD1_L EVEL_HIGH 12 GPIO_QSPI_SD1_L EVEL_LOW 11 GPIO_QSPI_SD0_E DGE_HIGH 10 GPIO_QSPI_SD0_E DGE_LOW 9 GPIO_QSPI_SD0_L EVEL_HIGH 8 GPIO_QSPI_SD0_L EVEL_LOW 7 GPIO_QSPI_SS_ED GE_HIGH 6 GPIO
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RP2040 Datasheet Bits Name 22 GPIO_QSPI_SD3_E Description Type Reset RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 DGE_LOW 21 GPIO_QSPI_SD3_L EVEL_HIGH 20 GPIO_QSPI_SD3_L EVEL_LOW 19 GPIO_QSPI_SD2_E DGE_HIGH 18 GPIO_QSPI_SD2_E DGE_LOW 17 GPIO_QSPI_SD2_L EVEL_HIGH 16 GPIO_QSPI_SD2_L EVEL_LOW 15 GPIO_QSPI_SD1_E DGE_HIGH 14 GPIO_QSPI_SD1_E DGE_LOW
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RP2040 Datasheet Bits Name 1 GPIO_QSPI_SCLK_ Description Type Reset RW 0x0 RW 0x0 LEVEL_HIGH 0 GPIO_QSPI_SCLK_ LEVEL_LOW PROC0_INTS Register Description Interrupt status after masking & forcing for proc0 Table 327. PROC0_INTS Register Bits Name Description Type Reset 31:24 Reserved.
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RP2040 Datasheet Bits Name 7 GPIO_QSPI_SS_ED Description Type Reset RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 GE_HIGH 6 GPIO_QSPI_SS_ED GE_LOW 5 GPIO_QSPI_SS_LE VEL_HIGH 4 GPIO_QSPI_SS_LE VEL_LOW 3 GPIO_QSPI_SCLK_ EDGE_HIGH 2 GPIO_QSPI_SCLK_ EDGE_LOW 1 GPIO_QSPI_SCLK_ LEVEL_HIGH 0 GPIO_QSPI_SCLK_ LEVEL_LOW PROC1_INTE Register Description Interrupt Enable for proc1 Table 328. PROC1_INTE Register Bits Name Description Type Reset 31:24 Reserved.
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RP2040 Datasheet Bits Name 13 GPIO_QSPI_SD1_L Description Type Reset RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 EVEL_HIGH 12 GPIO_QSPI_SD1_L EVEL_LOW 11 GPIO_QSPI_SD0_E DGE_HIGH 10 GPIO_QSPI_SD0_E DGE_LOW 9 GPIO_QSPI_SD0_L EVEL_HIGH 8 GPIO_QSPI_SD0_L EVEL_LOW 7 GPIO_QSPI_SS_ED GE_HIGH 6 GPIO_QSPI_SS_ED GE_LOW 5 GPIO_QSPI_SS_LE VEL_HIGH 4 GPIO_QSPI_SS_LE VEL_LOW 3 GPIO_QSPI_SCLK_ EDGE_HIGH 2 GPIO_Q
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RP2040 Datasheet Bits Name 19 GPIO_QSPI_SD2_E Description Type Reset RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 DGE_HIGH 18 GPIO_QSPI_SD2_E DGE_LOW 17 GPIO_QSPI_SD2_L EVEL_HIGH 16 GPIO_QSPI_SD2_L EVEL_LOW 15 GPIO_QSPI_SD1_E DGE_HIGH 14 GPIO_QSPI_SD1_E DGE_LOW 13 GPIO_QSPI_SD1_L EVEL_HIGH 12 GPIO_QSPI_SD1_L EVEL_LOW 11 GPIO_QSPI_SD0_E DGE_HIGH 10 GP
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RP2040 Datasheet Description Interrupt status after masking & forcing for proc1 Table 330. PROC1_INTS Register Bits Name Description Type Reset 31:24 Reserved.
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RP2040 Datasheet Bits Name 3 GPIO_QSPI_SCLK_ Description Type Reset RO 0x0 RO 0x0 RO 0x0 RO 0x0 EDGE_HIGH 2 GPIO_QSPI_SCLK_ EDGE_LOW 1 GPIO_QSPI_SCLK_ LEVEL_HIGH 0 GPIO_QSPI_SCLK_ LEVEL_LOW DORMANT_WAKE_INTE Register Description Interrupt Enable for dormant_wake Table 331. DORMANT_WAKE_INT E Register Bits Name Description Type Reset 31:24 Reserved.
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RP2040 Datasheet Bits Name 9 GPIO_QSPI_SD0_L Description Type Reset RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 EVEL_HIGH 8 GPIO_QSPI_SD0_L EVEL_LOW 7 GPIO_QSPI_SS_ED GE_HIGH 6 GPIO_QSPI_SS_ED GE_LOW 5 GPIO_QSPI_SS_LE VEL_HIGH 4 GPIO_QSPI_SS_LE VEL_LOW 3 GPIO_QSPI_SCLK_ EDGE_HIGH 2 GPIO_QSPI_SCLK_ EDGE_LOW 1 GPIO_QSPI_SCLK_ LEVEL_HIGH 0 GPIO_QSPI_SCLK_ LEVEL_LOW DORMANT_WAKE_INTF Register Description Interrupt Force for dormant_wake Tab
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RP2040 Datasheet Bits Name 15 GPIO_QSPI_SD1_E Description Type Reset RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 DGE_HIGH 14 GPIO_QSPI_SD1_E DGE_LOW 13 GPIO_QSPI_SD1_L EVEL_HIGH 12 GPIO_QSPI_SD1_L EVEL_LOW 11 GPIO_QSPI_SD0_E DGE_HIGH 10 GPIO_QSPI_SD0_E DGE_LOW 9 GPIO_QSPI_SD0_L EVEL_HIGH 8 GPIO_QSPI_SD0_L EVEL_LOW 7 GPIO_QSPI_SS_ED GE_HIGH 6 GPIO_QSPI_SS_ED GE_LOW 5 GPIO_QSPI_SS_LE
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RP2040 Datasheet Bits Name 21 GPIO_QSPI_SD3_L Description Type Reset RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 EVEL_HIGH 20 GPIO_QSPI_SD3_L EVEL_LOW 19 GPIO_QSPI_SD2_E DGE_HIGH 18 GPIO_QSPI_SD2_E DGE_LOW 17 GPIO_QSPI_SD2_L EVEL_HIGH 16 GPIO_QSPI_SD2_L EVEL_LOW 15 GPIO_QSPI_SD1_E DGE_HIGH 14 GPIO_QSPI_SD1_E DGE_LOW 13 GPIO_QSPI_SD1_L EVEL_HI
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RP2040 Datasheet Bits Name 0 GPIO_QSPI_SCLK_ Description Type Reset RO 0x0 LEVEL_LOW 2.18.6.3. Pad Control - User Bank Table 334. List of PADS_BANK0 registers 2.18. GPIO Offset Name Info 0x00 VOLTAGE_SELECT Voltage select.
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RP2040 Datasheet Offset Name 0x78 GPIO29 0x7c SWCLK 0x80 SWD Info VOLTAGE_SELECT Register Description Voltage select. Per bank control Table 335. VOLTAGE_SELECT Register Bits Name Description Type Reset 31:1 Reserved. - - - 0 NONAME 0x0 -> Set voltage to 3.3V (DVDD >= 2V5) RW 0x0 0x1 -> Set voltage to 1.8V (DVDD <= 1V8) GPIO0, GPIO1, …, GPIO28, GPIO29 Registers Table 336. GPIO0, GPIO1, …, GPIO28, GPIO29 Registers Bits Name Description Type Reset 31:8 Reserved.
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RP2040 Datasheet Bits Name Description Type Reset 2 PDE Pull down enable RW 0x0 1 SCHMITT Enable schmitt trigger RW 0x1 0 SLEWFAST Slew rate control. 1 = Fast, 0 = Slow RW 0x0 SWD Register Table 338. SWD Register Bits Name Description Type Reset 31:8 Reserved. - - - 7 OD Output disable. Has priority over output enable from RW 0x0 peripherals 6 IE Input enable RW 0x1 5:4 DRIVE Drive strength.
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RP2040 Datasheet Table 340. VOLTAGE_SELECT Register Bits Name Description Type Reset 31:1 Reserved. - - - 0 NONAME 0x0 -> Set voltage to 3.3V (DVDD >= 2V5) RW 0x0 0x1 -> Set voltage to 1.8V (DVDD <= 1V8) GPIO_QSPI_SCLK Register Table 341. GPIO_QSPI_SCLK Register Bits Name Description Type Reset 31:8 Reserved. - - - 7 OD Output disable. Has priority over output enable from RW 0x0 peripherals 6 IE Input enable RW 0x1 5:4 DRIVE Drive strength.
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RP2040 Datasheet Bits Name Description Type Reset 6 IE Input enable RW 0x1 5:4 DRIVE Drive strength. RW 0x1 0x0 -> 2mA 0x1 -> 4mA 0x2 -> 8mA 0x3 -> 12mA 3 PUE Pull up enable RW 0x1 2 PDE Pull down enable RW 0x0 1 SCHMITT Enable schmitt trigger RW 0x1 0 SLEWFAST Slew rate control. 1 = Fast, 0 = Slow RW 0x0 2.19. Sysinfo 2.19.1. Overview The sysinfo block contains system information.
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RP2040 Datasheet Table 347. GITREF_RP2040 Register Bits Name 31:0 NONAME Description Type Reset RO - 2.20. Syscfg 2.20.1.
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RP2040 Datasheet Offset Name Info 0x18 MEMPOWERDOWN Control power downs to memories. Set high to power down memories. Use with extreme caution PROC0_NMI_MASK Register Description Processor core 0 NMI source mask Table 349. PROC0_NMI_MASK Register Bits Name Description Type Reset 31:0 NONAME Set a bit high to enable NMI from that IRQ RW 0x00000000 PROC1_NMI_MASK Register Description Processor core 1 NMI source mask Table 350.
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RP2040 Datasheet Table 352. PROC_IN_SYNC_BYPA SS Register Bits Name Description Type Reset 31:30 Reserved. - - - 29:0 NONAME RW 0x00000000 PROC_IN_SYNC_BYPASS_HI Register Description For each bit, if 1, bypass the input synchronizer between that GPIO and the GPIO input register in the SIO. The input synchronizers should generally be unbypassed, to avoid injecting metastabilities into processors. If you’re feeling brave, you can bypass to save two cycles of input latency.
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RP2040 Datasheet 2.20.
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RP2040 Datasheet Chapter 3. PIO 3.1. Overview Figure 36. PIO blocklevel diagram. There are two PIO blocks with four state machines each. The four state machines simultaneously execute programs from a shared instruction memory. FIFO data queues buffer data transferred between PIO and the system. GPIO mapping logic allows each state machine to observe and manipulate up to 30 GPIOs. The programmable input/output block (PIO) is a versatile hardware interface.
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RP2040 Datasheet • IRQ flag set/clear/status Each state machine, along with its supporting hardware, occupies approximately the same silicon area as a standard serial interface block, such as an SPI or I2C controller. However, PIO state machines can be configured and reconfigured dynamically to implement numerous different interfaces.
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RP2040 Datasheet Though the PIO only has a total of nine instructions, it would be difficult to edit PIO program binaries by hand. PIO assembly is a textual format, describing a PIO program, where each command corresponds to one instruction in the output binary. Below is an example program in PIO assembly: 1 .
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RP2040 Datasheet 1 // Set the state machine running 2 hw_set_bits(&pio->ctrl, 1 << (PIO_CTRL_SM_ENABLE_LSB + 0)); The above code fragments are part of a complete application which drives a 12 MHz square wave out of GPIO 0.
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RP2040 Datasheet Autopull (see Section 3.5.4) allows the hardware to automatically refill the OSR in the majority of cases, with the state machine stalling if it tries to OUT from an empty OSR. This has two benefits: • No instructions spent on explicitly pulling from FIFO at the right time • Higher throughput: can output up to 32 bits on every single clock cycle, if the FIFO stays topped up After configuring autopull, the above program can be simplified to the following, which behaves identically: 1 .
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RP2040 Datasheet • The ISR can be automatically emptied once some number of bits have been shifted in. See Section 3.5.4 • PUSH or PULL instructions can be conditioned on the input or output shift counter, respectively On PIO reset, or the assertion of CTRL_SM_RESTART, the ISR shift counter is cleared to 0 (nothing yet shifted in), and the OSR shift counter is initialised to 32 (nothing remaining to be shifted out).
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RP2040 Datasheet Often, a state machine is only transferring data in one direction. In this case the SHIFTCTRL_FJOIN option can merge the two FIFOs into a single 8-entry FIFO going in one direction only. This is useful for high-bandwidth interfaces such as DPI. 3.2.4.
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RP2040 Datasheet 3.2.7. Interactions Between State Machines The instruction memory is implemented as a 1-write 4-read register file, so all four state machines can read an instruction on the same cycle, without stalling. There are three ways to apply the multiple state machines: • Pointing multiple state machines at the same program • Pointing multiple state machines at different programs • Using multiple state machines to run different parts of the same interface, e.g.
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RP2040 Datasheet  NOTE Within the Pico SDK you do not need to invoke pioasm directly, as the CMake function pico_generate_pio_header(TARGET PIO_FILE) takes care of invoking pioasm and adding the generated header to the include path of the target TARGET for you. 3.3.2. Directives The following directives control the assembly of PIO programs: Table 356. pioasm directives .define ( PUBLIC ) Define an integer symbol named with the value (see Section 3.3.3). If this .
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RP2040 Datasheet Table 357. Values in pioasm, i.e. integer An integer value e.g. 3 or -7 hex A hexidecimal value e.g. 0xf binary A binary value e.g. 0b1001 symbol A value defined by a .define (see [pioasm_define]) The instruction offset of the label within the program. This makes most sense when used with a JMP instruction (see Section 3.4.2) ( ) An expression to be evaluated; see expressions. Note that the parentheses are necessary. 3.3.4.
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RP2040 Datasheet (side ) ([]) where: Is an assembly instruction detailed in the following sections. (See Section 3.4) Is a value (see Section 3.3.3) to apply to the side_set pins at the start of the instruction. Note that the rules for a side set value via side are dependent on the .side_set (see [pioasm_side_set]) directive for the program. If no .
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RP2040 Datasheet This facility allows you to encapsulate both the PIO program and the associated setup required in the same source file. See Section 3.3.9 for a more complete example. 3.3.9. Language generators The following example shows a multi program source file (with multiple programs) which we will use to highlight c-sdk and python output features Pico Examples: https://github.com/raspberrypi/pico-examples/tree/pre_release/pio/ws2812/ws2812.
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RP2040 Datasheet 51 52 .define public T1 2 53 .define public T2 5 54 .define public T3 3 55 56 .wrap_target 57 out x, 32 58 mov pins, !null [T1-1] 59 mov pins, x [T2-1] 60 mov pins, null [T3-2] 61 .wrap 62 63 % c-sdk { 64 #include "hardware/clocks.
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RP2040 Datasheet 9 #endif 10 11 // ------ // 12 // ws2812 // 13 // ------ // 14 15 #define ws2812_wrap_target 0 16 #define ws2812_wrap 3 17 18 #define ws2812_T1 2 19 #define ws2812_T2 5 20 #define ws2812_T3 3 21 22 static const uint16_t ws2812_program_instructions[] = { 23 // 24 0x6221, // .wrap_target 0: out x, 1 side 0 [2] 25 0x1123, // 1: jmp !x, 3 side 1 [1] 26 0x1400, // 2: jmp 0 side 1 [4] 27 0xa442, // 3: nop 28 // side 0 [4] .
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RP2040 Datasheet 71 #define ws2812_parallel_T2 5 72 #define ws2812_parallel_T3 3 73 74 static const uint16_t ws2812_parallel_program_instructions[] = { 75 // 76 0x6020, // .wrap_target 0: out x, 32 77 0xa10b, // 1: mov pins, !null [1] 78 0xa401, // 2: mov pins, x [4] 79 0xa103, // 3: mov pins, null [1] 80 // .wrap 81 }; 82 83 #if !PICO_NO_HARDWARE 84 static const struct pio_program ws2812_parallel_program = { 85 .instructions = ws2812_parallel_program_instructions, 86 .
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RP2040 Datasheet  TIP The python language output is provided as a utility. MicroPython supports programming with the PIO natively, so you may only want to use pioasm when sharing PIO code between the Pico SDK and MicroPython. No effort is currently made to preserve label names, synmbols or comments, as it is assumed you are either using the PIO file as a source or python; not both. The python language output can of course be used to bootstrap your MicroPython PIO development based on an existing PIO file.
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RP2040 Datasheet 3.3.9.3. hex The hex generator only supports a single input program, as it just dumps the raw instructions (one per line) as a 4 bit hexidecimal number. Given: Pico Examples: https://github.com/raspberrypi/pico-examples/tree/pre_release/pio/squarewave/squarewave.pio Lines 1 - 12 1 ; 2 ; Copyright (c) 2020 Raspberry Pi (Trading) Ltd. 3 ; 4 ; SPDX-License-Identifier: BSD-3-Clause 5 ; 6 7 .
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RP2040 Datasheet The Delay/side-set field is present in all instructions. Its exact use is configured for each state machine by PINCTRL_SIDESET_COUNT: • Up to 5 MSBs encode a side-set operation (section Section 3.5.1), which optionally asserts a constant value onto some GPIOs, concurrently with main instruction execution logic • Remaining LSBs (up to 5) encode the number of idle cycles inserted between this instruction and the next 3.4.2. JMP 3.4.2.1.
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RP2040 Datasheet Is a program label or value (see Section 3.3.3) representing instruction offset within the program (the first instruction being offset 0). Note that because the PIO JMP instruction uses absolute addresses in the PIO instruction memory, JMPs need to be adjusted based on the program load offset at runtime. This is handled for you when loading a program with the Pico SDK, but care should be taken when encoding JMP instructions for use by OUT EXEC 3.4.3. WAIT 3.4.3.1.
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RP2040 Datasheet  CAUTION WAIT 1 IRQ x should not be used with IRQ flags presented to the interrupt controller, to avoid a race condition with a system interrupt handler 3.4.3.3. Assembler Syntax wait gpio wait pin wait irq ( rel ) where: Is a value (see Section 3.3.3) specifying the polarity (either 0 or 1) Is a value (see Section 3.3.
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RP2040 Datasheet (SHIFTCTRL_PUSH_THRESH). IN still executes in one cycle, whether an automatic push takes place or not. The state machine will stall if the RX FIFO is full when an automatic push occurs. An automatic push clears the ISR contents to all-zeroes, and clears the input shift count. See section Section 3.5.4. IN always uses the least significant Bit count bits of the source data.
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RP2040 Datasheet PINS and PINDIRS use the OUT pin mapping, as described in section Section 3.5.6. If automatic pull is enabled, the OSR is automatically refilled from the TX FIFO if the pull threshold, SHIFTCTRL_PULL_THRESH, is reached. The output shift count is simultaneously cleared to 0. In this case, the OUT will stall if the TX FIFO is empty, but otherwise still executes in one cycle. The specifics are given in section Section 3.5.4.
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RP2040 Datasheet Is equivalent to Block == 0 above. noblock 3.4.7. PULL 3.4.7.1. Encoding Bit: 15 14 13 PULL 1 0 0 12 11 10 9 8 Delay/side-set 7 6 5 4 3 2 1 0 1 IfE Blk 0 0 0 0 0 3.4.7.2. Operation Load a 32-bit word from the TX FIFO into the OSR. • IfEmpty: If 1, do nothing unless the total output shift count has reached its threshold, SHIFTCTRL_PULL_THRESH (the same as for autopull; see section Section 3.5.4). • Block: If 1, stall if TX FIFO is empty.
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RP2040 Datasheet 3.4.8.2. Operation Copy data from Source to Destination. • Destination: ◦ 000: PINS (Uses same pin mapping as OUT) ◦ 001: X (Scratch register X) ◦ 010: Y (Scratch register Y) ◦ 011: Reserved ◦ 100: EXEC (Execute data as instruction) ◦ 101: PC ◦ 110: ISR (Input shift counter is reset to 0 by this operation, i.e. empty) ◦ 111: OSR (Output shift counter is reset to 0 by this operation, i.e.
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RP2040 Datasheet If present, is: ! or ~ for NOT (Note: this is always a bitwise NOT) :: for bit reverse Is one of the sources specified above. 3.4.9. IRQ 3.4.9.1. Encoding Bit: 15 14 13 IRQ 1 1 0 12 11 10 9 Delay/side-set 8 7 6 5 0 Clr Wait 4 3 2 1 0 Index 3.4.9.2. Operation Set or clear the IRQ flag selected by Index argument. • Clear: if 1, clear the flag selected by Index, instead of raising it. If Clear is set, the Wait bit has no effect.
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RP2040 Datasheet irq set Also means set the IRQ without waiting irq nowait Again, means set the IRQ without waiting irq wait Means set the IRQ and wait for it to be cleared before proceeding irq clear Means clear the IRQ 3.4.10. SET 3.4.10.1. Encoding Bit: 15 14 13 SET 1 1 1 12 11 10 9 8 Delay/side-set 7 6 5 4 Destination 3 2 1 0 Data 3.4.10.2. Operation Write immediate value Data to Destination.
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RP2040 Datasheet 3.5. Functional Details 3.5.1. Side-set Side-set is a feature that allows state machines to change the level or direction of up to 5 pins, concurrently with the main execution of the instruction. One example where this is necessary is a fast SPI interface: here a clock transition (toggling 1->0 or 0->1) must be simultaneous with a data transition, where a new data bit is shifted from the OSR to a GPIO. In this case an OUT with a side-set would achieve both of these at once.
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RP2040 Datasheet 4. Whether side-set writes to GPIO levels or GPIO directions. Configured by EXECCTRL_SIDE_PINDIR In the above example, we have only one side-set data bit, and every instruction performs a side-set, so no enable bit is required. SIDESET_COUNT would be 1, SIDE_EN would be false. SIDE_PINDIR would also be false, as we want to drive the clock high and low, not high- and low-impedance. SIDESET_BASE would select the GPIO the clock is driven from. 3.5.2.
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RP2040 Datasheet 8 #define squarewave_wrap_wrap_target 0u 9 #define squarewave_wrap_wrap 1u The squarewave_wrap example has delay cycles inserted, so that it behaves identically to the original squarewave program. Thanks to program wrapping, these can be removed, so that the output toggles twice as fast, while maintaining an even balance of high and low periods. 1 .program squarewave_fast 2 3 .wrap_target 4 set pins, 1 ; Drive pin high 5 set pins, 0 ; Drive pin low 6 .wrap 3.5.3.
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RP2040 Datasheet  CAUTION Changing FJOIN discards any data present in the state machine’s FIFOs. If this data is irreplaceable, it must be drained beforehand. 3.5.4. Autopush and Autopull With each OUT instruction, the OSR gradually empties, as data is shifted out. Once empty, it must be refilled: for example, a PULL transfers one word of data from the TX FIFO to the OSR. Similarly, the ISR must be emptied once full.
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RP2040 Datasheet 1 .program autopull 2 .side_set 1 3 4 .wrap_target 5 out pins, 1 side 0 [1] 6 nop side 1 [1] 7 .wrap This is shorter and simpler than the original, and can run twice as fast, if the delay cycles are removed, since the hardware refills the OSR "for free".
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RP2040 Datasheet 18 mm_pio->instr_mem[i] = auto_push_pull_program[i]; 19 mm_pio->sm[0].shiftctrl = 20 (1u << PIO_SM0_SHIFTCTRL_AUTOPUSH_LSB) | 21 (1u << PIO_SM0_SHIFTCTRL_AUTOPULL_LSB) | 22 (0u << PIO_SM0_SHIFTCTRL_PUSH_THRESH_LSB) | 23 (0u << PIO_SM0_SHIFTCTRL_PULL_THRESH_LSB); 24 mm_pio->sm[0].
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RP2040 Datasheet 3.5.4.1. Autopush Details Pseudocode for an 'IN' with autopush enabled: 1 isr = shift_in(isr, input()) 2 isr count = saturate(isr count + in count) 3 4 if rx count >= threshold: 5 if rx fifo is full: 6 7 stall else: 8 push(isr) 9 isr = 0 10 isr count = 0 Note that the hardware performs the above steps in a single machine clock cycle (unless there is a stall). Threshold is configurable from 1 to 32. 3.5.4.2.
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RP2040 Datasheet Note that a 'MOV' from the OSR is undefined whilst autopull is enabled; you will read either any residual data that has not been shifted out, or a fresh word from the FIFO, depending on a race against system DMA. Likewise, a 'MOV' to the OSR may overwrite data which has just been autopulled. However, data which you 'MOV' into the OSR will never be overwritten, since 'MOV' updates the shift counter. If you do need to read the OSR contents, you should perform an explicit 'PULL' of some kind.
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RP2040 Datasheet Figure 45. Fractional clock division with an average divisor of 2.5. The clock divider maintains a running total of the fractional value from each System Clock CLKDIV_INT 2 CLKDIV_FRAC .5 CTRL_SM_ENABLE Clock Enable division period, and every time this value wraps through 1, the integer divisor is increased by one for the next division period. For small n, the jitter introduced by a fractional divider may be unacceptable.
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RP2040 Datasheet on this request, and the pin mapping configuration. If a side-set overlaps with an OUT/SET performed by that state machine on the same cycle, the side-set takes precedence in the overlapping region. 3.5.6.1. Output Priority Figure 47. Per-GPIO priority select of write masks from each state machine. Each GPIO considers level and direction writes from each of the four state machines, and applies the value from the highest-numbered state machine.
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RP2040 Datasheet  WARNING Sampling a metastable input can lead to unpredictable state machine behaviour. This should be avoided. 3.5.7. Forced and EXEC’d Instructions Besides the instruction memory, state machines can execute instructions from 3 other sources: • MOV EXEC which executes an instruction from some register Source • OUT EXEC which executes data shifted out from the OSR • The SMx_INSTR control registers, to which the system can write instructions for immediate execution 1 .
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RP2040 Datasheet 30 mm_pio->txf[0] = instructions_to_push_program[2]; // push 31 32 // The program pushed into TX FIFO will return some data in RX FIFO 33 while (mm_pio->fstat & (1u << PIO_FSTAT_RXEMPTY_LSB)) 34 ; 35 36 printf("%d\n", mm_pio->rxf[0]); 37 38 return 0; 39 } Here we load an example program into the state machine, which does two things: • Enters an infinite loop • Enters a loop which repeatedly pops 32 bits of data from the TX FIFO, and executes the lower 16 bits as an instructio
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RP2040 Datasheet Figure 48. In SPI, a Chip Select host and device exchange data over a bidirectional pair of SDO/SDI serial data lines, 7 6 5 4 3 2 1 0 synchronous with a CPHA=0 CPOL=0 clock (SCK). Two flags, CPOL and CPHA, specify the CPHA=0 CPOL=1 clock’s behaviour. CPOL is the idle state of the clock: 0 for low, 1 for high.
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RP2040 Datasheet  NOTE These programs do not control the chip select line; chip select is often implemented as a software-controlled GPIO, due to wildly different behaviour between different SPI hardware. The full spi.pio source linked above contains some examples how PIO can implement a hardware chip select line. A C helper function configures the state machine, connects the GPIOs, and sets the state machine running.
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RP2040 Datasheet 28 } 29 if (rx_remain && !pio_sm_is_rx_empty(spi->pio, spi->sm)) { 30 (void) *rxfifo; 31 --rx_remain; 32 } 33 } 34 } Putting this all together, this complete C program will loop back some data through a PIO SPI at 1 MHz, with all four CPOL/CPHA combinations: Pico Examples: https://github.com/raspberrypi/pico-examples/tree/pre_release/pio/spi/spi_loopback.c Lines 1 - 77 1 /** 2 * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
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RP2040 Datasheet 50 setup_default_uart(); 51 52 pio_spi_inst_t spi = { 53 .pio = pio0, 54 .sm = 0 55 }; 56 float clkdiv = 31.25f; 57 uint cpha0_prog_offs = pio_add_program(spi.pio, &spi_cpha0_program); 58 uint cpha1_prog_offs = pio_add_program(spi.pio, &spi_cpha1_program); // 1 MHz @ 125 clk_sys 59 60 for (int cpha = 0; cpha <= 1; ++cpha) { 61 for (int cpol = 0; cpol <= 1; ++cpol) { 62 printf("CPHA = %d, CPOL = %d\n", cpha, cpol); 63 pio_spi_init(spi.pio, spi.
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RP2040 Datasheet each data bit. Autopull must be configured, with a threshold of 24. Software can then write 24-bit pixel values into the FIFO, and these will be serialised to a chain of WS2812 LEDs. 1 #include "tb.h" 2 #include "gpio.h" 3 #include "pio.h" 4 #include "pio/stdio.pio.h" 5 6 #include
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RP2040 Datasheet 60 const int PIN_TX = 0; 61 62 int main() 63 { 64 tb_init(); 65 66 puts("WS2812 Smoke Test"); 67 68 pio_sm_init(pio0, 0); 69 pio_load_program_arr(pio0, ws2812_program, 0); 70 pio_setup_shiftctrl(pio0, 0, SHIFT_TO_RIGHT, SHIFT_TO_LEFT, false, true, 32, 24); 71 pio_set_clkdiv_int_frac(pio0, 0, 5, 0); 72 pio_setup_pinctrl(pio0, 0, 0, 0, 0, 0, PIN_TX, 0); 73 pio_setup_sideset(pio0, 0, 1, false, false); 74 pio_set_wrap(pio0, 0, ws2812_wrap_target, ws2812_wrap); 75 pio_sm_enab
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RP2040 Datasheet 3.6.3. UART TX Figure 50. UART serial Bit Clock format. The line is 0 TX high when idle. The transmitter pulls the State Idle 1 Start 2 3 4 5 6 7 Data (LSB first) Stop line down for one bit period to signify the start of a serial frame (the "start bit"), and a small, fixed number of This program implements the transmit component of a universal asynchronous receive/transmit (UART) serial peripheral. Perhaps it would be more correct to refer to this as a UAT.
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RP2040 Datasheet 39 sm_config_set_sideset_pins(&c, pin_tx); 40 41 // We only need TX, so get an 8-deep FIFO! 42 sm_config_set_fifo_join(&c, PIO_FIFO_JOIN_TX); 43 44 // SM transmits 1 bit per 8 execution cycles. 45 float div = (float)clock_get_hz(clk_sys) / (8 * baud); 46 sm_config_set_clkdiv(&c, div); 47 48 pio_sm_init(pio, sm, offset, &c); 49 pio_sm_enable(pio, sm, true); 50 } The state machine is configured to shift right in out instructions, because UARTs typically send data LSB-first.
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RP2040 Datasheet 25 26 sleep_ms(1000); } 27 } With the two PIO instances on RP2040, this could be extended to 8 additional UART TX interfaces, on 8 different pins, with 8 different baud rates. 3.6.4. UART RX Recalling figure Figure 50 showing the format of an 8n1 UART: Bit Clock 0 TX State Idle 1 2 Start 3 4 5 6 7 Data (LSB first) Stop We can recover the data by waiting for the start bit, sampling 8 times with the correct timing, and pushing the result to the RX FIFO.
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RP2040 Datasheet 60 61 good_stop: ; No delay before returning to start; a little slack is 62 ; important in case the TX clock is slightly too fast. push The second example does not use autopush (Section 3.5.4), preferring instead to use an explicit push instruction, so that it can condition the push on whether a correct stop bit is seen. The .pio file includes a helper function which configures the state machine and connects it to a GPIO with the pullup enabled: Pico Examples: https://github.
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RP2040 Datasheet 2 * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include 8 9 #include "pico/stdlib.h" 10 #include "pico/multicore.h" 11 #include "hardware/pio.h" 12 #include "hardware/uart.h" 13 #include "uart_rx.pio.
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RP2040 Datasheet 3.6.5. Manchester Serial TX and RX Figure 51. Manchester Data Idle 0 0 1 1 0 1 serial line code. Each data bit is represented Line by either a high pulse followed by a low pulse (representing a Pico Examples: https://github.com/raspberrypi/pico-examples/tree/pre_release/pio/manchester_encoding/manchester_encoding.pio Lines 7 - 29 '0' bit) or a low pulse followed by a high pulse (a '1' bit). 7 .program manchester_tx 8 .side_set 1 opt 9 10 ; Transmit one bit every 12 cycles.
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RP2040 Datasheet Pico Examples: https://github.com/raspberrypi/pico-examples/tree/pre_release/pio/manchester_encoding/manchester_encoding.pio Lines 48 - 70 48 .program manchester_rx 49 50 ; Assumes line is idle low, first bit is 0 51 ; One bit is 12 cycles 52 ; a '0' is encoded as 10 53 ; a '1' is encoded as 01 54 ; 55 ; Both the IN base and the JMP pin mapping must be pointed at the GPIO used for RX. 56 ; Autopush must be enabled.
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RP2040 Datasheet The example C program in the SDK will transmit Manchester serial data from GPIO2 to GPIO3 at approximately 10 Mbps (assuming a system clock of 125 MHz). Pico Examples: https://github.com/raspberrypi/pico-examples/tree/pre_release/pio/manchester_encoding/manchester_encoding.
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RP2040 Datasheet 20 jmp !x high_0 [6] ; Test the data bit we just shifted out of OSR 21 high_1: 22 jmp initial_high side 0 [7] ; For `1` bits, also transition in the middle 23 high_0: 24 jmp initial_low [7] ; Otherwise, the line is stable in the middle 25 26 initial_low: 27 out x, 1 28 jmp !x low_0 side 0 ; Always shift 1 bit from OSR to X so we can [6] ; branch on it. Autopull refills OSR for us.
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RP2040 Datasheet 61 62 public start: 63 initial_high: 64 wait 1 pin, 0 65 jmp pin high_0 ; Find rising edge at start of bit period [11] ; Delay to eye of second half-period (i.e 3/4 of way ; through bit) and branch on RX pin high/low. 66 high_1: 67 in x, 1 68 jmp initial_high ; Second transition detected (a `1` data symbol) 69 high_0: 70 in y, 1 [1] 71 ; Fall-through ; Line still high, no centre transition (data is `0`) 72 73 .
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RP2040 Datasheet 10 #include "hardware/pio.h" 11 #include "differential_manchester.pio.
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RP2040 Datasheet 17 jmp y-- incr 18 mov isr, ~x 19 push A full 32-bit addition takes only around one minute at 125 MHz. The program pops two numbers from the TX FIFO and pushes their sum to the RX FIFO, which is perfect for use either with the system DMA, or directly by the processor: Pico Examples: https://github.com/raspberrypi/pico-examples/tree/pre_release/pio/addition/addition.c Lines 1 - 35 1 /** 2 * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
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RP2040 Datasheet  WARNING These examples are outdated, and may not reflect best practices, or even assemble under the latest pioasm — you are much better off looking at the code in pico-examples! This section will shrink with time and the "Examples" section will grow to replace it. TODO delete this section once each of these is replaced with a documented SDK example 3.7.1. UART with CTSn and RTSn 1 .program uart_tx_cts 2 .side_set 1 opt 3 4 .
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RP2040 Datasheet 1 .side_set 1 opt ; 1-bit wide side set, with an enable bit. 2 3 .wrap_target 4 out x, 8 5 mov y, isr ; pin will go high when we count down through this value side 0 ; preload counter to max value, and set pin low (simultaneous) 6 pwm_loop: 7 jmp x!=y skip 8 nop side 1 ; nop with side-set (could also use set, if mapping configured) 9 skip: 10 jmp y-- pwm_loop [14] 11 .
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RP2040 Datasheet 4 ; | high len | low len | (dither, continue) * n | 5 6 start: 7 out y, 7 ; Stash the two base pulse lengths 8 mov isr, y ; (ab)use ISR as 3rd scratch register 9 out y, 7 10 .wrap_target 11 out pins, 1 12 mov x, isr ; Dither is prepended to next 1, or appended to prev 0 side 1 13 loop1: 14 jmp x-- loop1 15 mov x, y side 0 16 loop0: 17 jmp x-- loop0 18 out x, 1 19 jmp !x start ; Branch on continue bit 20 nop [2] ; Ensure carrier freq is constant 21 .
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RP2040 Datasheet 9 ; The Instr mechanism allows stop/start/repstart sequences to be programmed 10 ; by the processor, and then carried out by the state machine at defined points 11 ; in the datastream. 12 ; 13 ; The "Final" field should be set for the final byte in a transfer. 14 ; This tells the state machine to ignore a NAK: if this field is not 15 ; set, then any NAK will cause the state machine to halt and interrupt. 16 ; 17 ; Autopull should be enabled, with a threshold of 16.
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RP2040 Datasheet 3.7.4. I2S 1 .program i2s_2x16 2 .side_set 2 3 4 ; Transmit a stereo I2S audio stream. 5 ; This is 16 bits per sample; can be altered by modifying the "set" params, 6 ; or made programmable by replacing "set x" with "mov x, y" and using Y as a config register. 7 ; 8 ; Autopull must be enabled, with threshold set to 32. 9 ; Since I2S is MSB-first, shift direction should be to left.
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RP2040 Datasheet acknowledgement 9 .wrap_top Note the use of relative IRQ addressing. Up to 4 of these interfaces could be instantiated on different pins, using the same instructions, and the processor would receive a separate interrupt from each. 3.7.6. APA102 LEDs APA102s have a 32-bit command syntax containing some constant bits, a global brightness config, and 24 bits of colour data.
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RP2040 Datasheet 3.8. List of Registers Table 360. List of PIO registers Offset Name Info 0x000 CTRL PIO control register 0x004 FSTAT FIFO status register 0x008 FDEBUG FIFO debug register 0x00c FLEVEL FIFO levels 0x010 TXF0 Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. 0x014 TXF1 Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO.
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RP2040 Datasheet Offset Name Info 0x044 DBG_CFGINFO The PIO hardware has some free parameters that may vary between chip products. These should be provided in the chip datasheet, but are also exposed here.
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RP2040 Datasheet Offset Name Info 0x0c8 SM0_CLKDIV Clock divider register for state machine 0 Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) 0x0cc SM0_EXECCTRL Execution/behavioural settings for state machine 0 0x0d0 SM0_SHIFTCTRL Control behaviour of the input/output shift registers for state machine 0 0x0d4 SM0_ADDR Current instruction address of state machine 0 0x0d8 SM0_INSTR Instruction currently being executed by state machine 0 Write to execute an instruction immediately
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RP2040 Datasheet Offset Name Info 0x12c IRQ0_INTE Interrupt Enable for irq0 0x130 IRQ0_INTF Interrupt Force for irq0 0x134 IRQ0_INTS Interrupt status after masking & forcing for irq0 0x138 IRQ1_INTE Interrupt Enable for irq1 0x13c IRQ1_INTF Interrupt Force for irq1 0x140 IRQ1_INTS Interrupt status after masking & forcing for irq1 CTRL Register Description PIO control register Table 361. CTRL Register Bits Name Description Type Reset 31:12 Reserved.
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RP2040 Datasheet Bits Name Description Type Reset 27:24 TXSTALL State machine has stalled on empty TX FIFO. Write 1 to WC 0x0 clear. 23:20 Reserved. - - - 19:16 TXOVER TX FIFO overflow has occurred. Write 1 to clear. WC 0x0 15:12 Reserved. - - - 11:8 RXUNDER RX FIFO underflow has occurred. Write 1 to clear. WC 0x0 7:4 Reserved. - - - 3:0 RXSTALL State machine has stalled on full RX FIFO. Write 1 to clear.
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RP2040 Datasheet Table 367. IRQ Register Bits Name Description Type Reset 31:8 Reserved. - - - 7:0 NONAME WC 0x00 IRQ_FORCE Register Description Writing a 1 to each of these bits will forcibly assert the corresponding IRQ. Note this is different to the INTF register: writing here affects PIO internal state. INTF just asserts the processor-facing IRQ signal for testing ISRs, and is not visible to the state machines. Table 368.
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RP2040 Datasheet Bits Name Description Type Reset 21:16 IMEM_SIZE The size of the instruction memory, measured in units of RO - one instruction 15:12 Reserved. - - - 11:8 SM_COUNT The number of state machines this PIO instance is RO - equipped with. 7:6 Reserved. - - - 5:0 FIFO_DEPTH The depth of the state machine TX/RX FIFOs, measured in RO - words. Joining fifos via SHIFTCTRL_FJOIN gives one FIFO with double this depth.
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RP2040 Datasheet Bits Name Description Type Reset 28:24 JMP_PIN The GPIO number to use as condition for JMP PIN. RW 0x00 Unaffected by input mapping. 23:19 OUT_EN_SEL Which data bit to use for inline OUT enable RW 0x00 18 INLINE_OUT_EN If 1, use a bit of OUT data as an auxiliary write enable RW 0x0 When used in conjunction with OUT_STICKY, writes with an enable of 0 will deassert the latest pin write.
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RP2040 Datasheet Bits Name Description Type 18 IN_SHIFTDIR 1 = shift input shift register to right (data enters from left). 0 RW Reset 0x1 = to left. 17 AUTOPULL Pull automatically when the output shift register is emptied RW 0x0 16 AUTOPUSH Push automatically when the input shift register is filled RW 0x0 15:0 Reserved. - - - SM0_ADDR, SM1_ADDR, SM2_ADDR, SM3_ADDR Registers Description Current instruction address of state machine N Table 377.
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RP2040 Datasheet Bits Name 11 Description Type Reset SM3 RO 0x0 10 SM2 RO 0x0 9 SM1 RO 0x0 8 SM0 RO 0x0 7 SM3_TXNFULL RO 0x0 6 SM2_TXNFULL RO 0x0 5 SM1_TXNFULL RO 0x0 4 SM0_TXNFULL RO 0x0 3 SM3_RXNEMPTY RO 0x0 2 SM2_RXNEMPTY RO 0x0 1 SM1_RXNEMPTY RO 0x0 0 SM0_RXNEMPTY RO 0x0 IRQ0_INTE Register Description Interrupt Enable for irq0 Table 381. IRQ0_INTE Register Bits Name Description Type Reset 31:12 Reserved.
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RP2040 Datasheet Bits Name 10 Description Type Reset SM2 RW 0x0 9 SM1 RW 0x0 8 SM0 RW 0x0 7 SM3_TXNFULL RW 0x0 6 SM2_TXNFULL RW 0x0 5 SM1_TXNFULL RW 0x0 4 SM0_TXNFULL RW 0x0 3 SM3_RXNEMPTY RW 0x0 2 SM2_RXNEMPTY RW 0x0 1 SM1_RXNEMPTY RW 0x0 0 SM0_RXNEMPTY RW 0x0 IRQ0_INTS Register Description Interrupt status after masking & forcing for irq0 Table 383. IRQ0_INTS Register Bits Name Description Type Reset 31:12 Reserved.
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RP2040 Datasheet Bits Name 9 Description Type Reset SM1 RW 0x0 8 SM0 RW 0x0 7 SM3_TXNFULL RW 0x0 6 SM2_TXNFULL RW 0x0 5 SM1_TXNFULL RW 0x0 4 SM0_TXNFULL RW 0x0 3 SM3_RXNEMPTY RW 0x0 2 SM2_RXNEMPTY RW 0x0 1 SM1_RXNEMPTY RW 0x0 0 SM0_RXNEMPTY RW 0x0 IRQ1_INTF Register Description Interrupt Force for irq1 Table 385. IRQ1_INTF Register Bits Name Description Type Reset 31:12 Reserved.
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RP2040 Datasheet Bits Name 8 Type Reset SM0 RO 0x0 7 SM3_TXNFULL RO 0x0 6 SM2_TXNFULL RO 0x0 5 SM1_TXNFULL RO 0x0 4 SM0_TXNFULL RO 0x0 3 SM3_RXNEMPTY RO 0x0 2 SM2_RXNEMPTY RO 0x0 1 SM1_RXNEMPTY RO 0x0 0 SM0_RXNEMPTY RO 0x0 3.8.
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RP2040 Datasheet Chapter 4. Peripherals 4.1. USB 4.1.1. Overview Prerequisite Knowledge Required This section requires knowledge of the USB protocol. We recommend [usbmadesimple] if you are unclear on the terminology used in this section (see References). RP2040 contains a USB 2.0 controller that can operate as either: • a Full Speed device (12 Mbit/s) • a host that can communicate with both Low Speed (1.5 Mbit/s) and Full Speed devices. This includes multiple downstream devices connected to a USB hub.
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RP2040 Datasheet Figure 53. A simplified overview of the USB controller architecture. The USB controller is an area efficient design that muxes a device controller or host controller onto a common set of components. Each component is detailed below. 4.1.2.1. USB PHY The USB PHY provides the electrical interface between the USB DP and DM pins and the digital logic of the controller.
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RP2040 Datasheet  NOTE If you disconnect the USB cable during a packet in either host or device mode you will see errors raised by the hardware. Your software will need to take this scenario into account if you enable error interrupts. 4.1.2.4. Serial TX Engine The serial transmit engine is a mirror of the serial receive engine. It is connected to the currently active controller (either device or host). It creates TOKEN and DATA packets, including calculating the CRC, and transmits them on the bus. 4.1.
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RP2040 Datasheet 4.1.
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RP2040 Datasheet Offset Device Function Host Function 0xd0 EP10 in buffer control Interrupt endpoint buffer control 10 0xd4 EP10 out buffer control Spare 0xd8 EP11 in buffer control Interrupt endpoint buffer control 11 0xdc EP11 out buffer control Spare 0xe0 EP12 in buffer control Interrupt endpoint buffer control 12 0xe4 EP12 out buffer control Spare 0xe8 EP13 in buffer control Interrupt endpoint buffer control 13 0xec EP13 out buffer control Spare 0xf0 EP14 in buffer control
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RP2040 Datasheet  NOTE The data buffer base address must be 64-byte aligned as bits 0-5 are ignored 4.1.2.5.3. Buffer control register The buffer control register contains information about the state of the data buffers for that endpoint. It is shared between the processor and the controller. If the endpoint is configured to be single buffered, only the first half (bits 0-15) of the buffer are used. If double buffering, the buffer select starts at buffer 0.
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RP2040 Datasheet 4.1.2.6.1. SETUP The device controller MUST always accept a setup packet from the host. That is why the first 8 bytes of the DPSRAM has dedicated space for the setup packet. The [usbspec] states that receiving a setup packet also clears any stall bits on EP0. For this reason, the stall bits for EP0 are gated with two bits in the EP_STALL_ARM register. These bits are cleared when a setup packet is received.
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RP2040 Datasheet • Is the AVAILABLE bit set and the FULL bit unset. If so go to the data phase, unless the STALL bit is set in which case the device controller will reply with a STALL. DATA phase: • Store received data in buffer. If Isochronous go to STATUS phase. Otherwise go to ACK phase. ACK phase: • Send ACK. Go to STATUS phase. STATUS phase: See status phase from Section 4.1.2.6.2.
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RP2040 Datasheet • SOF_SYNC - The SOF Sync bit is used to delay the transaction until after the next SOF. This is useful for interrupt and isochronous endpoints. The Host controller prevents a transaction of 64bytes from clashing with the SOF packets. For longer Isochronous packet the software is responsible for preventing a collision by using the SOF Sync bit and limiting the number of packets sent in one frame.
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RP2040 Datasheet  WARNING The USB host controller has a bug (RP2040-E4) that means the status written back to the buffer control register can appear in the wrong half of the register. Bits 0-15 are for buffer 0, and bits 16-31 are for buffer 1. The host controller has a buffer selector that is flipped after each transfer is complete. This buffer selector is incorrectly used when writing status information back to the buffer control register even in single buffered mode.
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RP2040 Datasheet • Set the address and endpoint of the device in the appropriate ADDR_ENDP register (ADDR_ENDP1 to ADDR_ENDP15). The preamble bit should be set if the device is Low Speed but attached to a Full Speed hub. The endpoint direction bit should also be set. • Set the interrupt endpoint active bit in INT_EP_CTRL (i.e. set bit 1 to 15 of that register) Typically an interrupt endpoint will be an IN transfer.
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RP2040 Datasheet Figure 54. USB analyser trace of the dev_lowlevel USB device example. The control transfers are the device enumeration. The first bulk OUT (out from the host) transfer, highlighted in blue, is the host sending "Hello World" to the device. The second bulk transfer IN (in to the host), is the device returning "Hello World" to the host. 4.1.3.2.1. Device controller initialisation The following code initialises the USB device. Pico Examples: https://github.
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RP2040 Datasheet 216 // Present full speed device by enabling pull up on DP 217 usb_hw_set->sie_ctrl = USB_SIE_CTRL_PULLUP_EN_BITS; 218 } 4.1.3.2.2. Configuring the endpoint control registers for EP1 and EP2 The function usb_configure_endpoints loops through each endpoint defined in the device configuration (including EP0 in and EP0 out, which don’t have an endpoint control register defined) and calls the usb_configure_endpoint function.
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RP2040 Datasheet 379 uint8_t req_direction = pkt->bmRequestType; 380 uint8_t req = pkt->bRequest; 381 382 // Reset PID to 1 for EP0 IN 383 usb_get_endpoint_configuration(EP0_IN_ADDR)->next_pid = 1u; 384 385 if (req_direction == USB_DIR_OUT) { 386 if (req == USB_REQUEST_SET_ADDRESS) { 387 usb_set_device_address(pkt); 388 } else if (req == USB_REQUEST_SET_CONFIGURATION) { 389 usb_set_device_configuration(pkt); 390 } else { 391 printf("Other OUT request (0x%x)\r\n", pkt->bRequest); 392 3
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RP2040 Datasheet control register. Once the buffer control register has been written to, the device controller will respond to the host with the data. Before this point, the device will reply with a NAK. Pico Examples: https://github.com/raspberrypi/pico-examples/tree/pre_release/usb/device/dev_lowlevel/dev_lowlevel.
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RP2040 Datasheet Offset Name Info 0x3c ADDR_ENDP15 Interrupt endpoint 15. Only valid for HOST mode. 0x40 MAIN_CTRL Main control register 0x44 SOF_WR Set the SOF (Start of Frame) frame number in the host controller. The SOF packet is sent every 1ms and the host will increment the frame number by 1 each time. 0x48 SOF_RD Read the last SOF (Start of Frame) frame number seen. In device mode the last SOF received from the host. In host mode the last SOF sent by the host.
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RP2040 Datasheet Offset Name Info 0x8c INTR Raw Interrupts 0x90 INTE Interrupt Enable 0x94 INTF Interrupt Force 0x98 INTS Interrupt status after masking & forcing ADDR_ENDP Register Description Device address and endpoint control Table 391. ADDR_ENDP Register Bits Name Description Type Reset 31:20 Reserved. - - - 19:16 ENDPOINT Device endpoint to send data to. Only valid for HOST mode. RW 0x0 15:7 Reserved.
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RP2040 Datasheet SOF_WR Register Description Set the SOF (Start of Frame) frame number in the host controller. The SOF packet is sent every 1ms and the host will increment the frame number by 1 each time. Table 394. SOF_WR Register Bits Name Description Type Reset 31:11 Reserved. - - - 10:0 COUNT WF 0x000 SOF_RD Register Description Read the last SOF (Start of Frame) frame number seen. In device mode the last SOF received from the host. In host mode the last SOF sent by the host. Table 395.
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RP2040 Datasheet Bits Name Description Type 12 RESUME Device: Remote wakeup. Device can initiate its own resume SC Reset 0x0 after suspend. 11 VBUS_EN Host: Enable VBUS RW 0x0 10 KEEP_ALIVE_EN Host: Enable keep alive packet (for low speed bus) RW 0x0 9 SOF_EN Host: Enable SOF generation (for full speed bus) RW 0x0 8 SOF_SYNC Host: Delay packet(s) until after SOF RW 0x0 7 Reserved. - - - 6 PREAMBLE_EN Host: Preable enable for LS device on FS hub RW 0x0 5 Reserved.
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RP2040 Datasheet Bits Name Description Type Reset 25 BIT_STUFF_ERRO Bit Stuff Error. Raised by the Serial RX engine. WC 0x0 R 24 CRC_ERROR CRC Error. Raised by the Serial RX engine. WC 0x0 23:20 Reserved. - - - 19 BUS_RESET Device: bus reset received WC 0x0 18 TRANS_COMPLET Transaction complete.
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RP2040 Datasheet BUFF_STATUS Register Description Buffer status register. A bit set here indicates that a buffer has completed on the endpoint (if the buffer interrupt is enabled). It is possible for 2 buffers to be completed, so clearing the buffer status bit may instantly re set it on the next clock cycle. Table 399. BUFF_STATUS Register 4.1.
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RP2040 Datasheet Bits Name 0 EP0_IN Description Type Reset RO 0x0 BUFF_CPU_SHOULD_HANDLE Register Description Which of the double buffers should be handled. Only valid if using an interrupt per buffer (i.e. not per 2 buffers). Not valid for host interrupt endpoint polling because they are only single buffered. Table 400. BUFF_CPU_SHOULD_H ANDLE Register 4.1.
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RP2040 Datasheet Bits Name 1 0 Description Type Reset EP0_OUT RO 0x0 EP0_IN RO 0x0 EP_ABORT Register Description Device only: Can be set to ignore the buffer control register for this endpoint in case you would like to revoke a buffer. A NAK will be sent for every access to the endpoint until this bit is cleared. A corresponding bit in EP_ABORT_DONE is set when it is safe to modify the buffer control register. Table 401. EP_ABORT Register 4.1.
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RP2040 Datasheet Bits Name 3 Description Type Reset EP1_OUT RW 0x0 2 EP1_IN RW 0x0 1 EP0_OUT RW 0x0 0 EP0_IN RW 0x0 EP_ABORT_DONE Register Description Device only: Used in conjunction with EP_ABORT. Set once an endpoint is idle so the programmer knows it is safe to modify the buffer control register. Table 402. EP_ABORT_DONE Register 4.1.
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RP2040 Datasheet Bits Name 4 Description Type Reset EP2_IN WC 0x0 3 EP1_OUT WC 0x0 2 EP1_IN WC 0x0 1 EP0_OUT WC 0x0 0 EP0_IN WC 0x0 EP_STALL_ARM Register Description Device: this bit must be set in conjunction with the STALL bit in the buffer control register to send a STALL on EP0. The device controller clears these bits when a SETUP packet is received because the USB spec requires that a STALL condition is cleared when a SETUP packet is received. Table 403.
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RP2040 Datasheet Bits Name 23 Description Type Reset EP11_OUT WC 0x0 22 EP11_IN WC 0x0 21 EP10_OUT WC 0x0 20 EP10_IN WC 0x0 19 EP9_OUT WC 0x0 18 EP9_IN WC 0x0 17 EP8_OUT WC 0x0 16 EP8_IN WC 0x0 15 EP7_OUT WC 0x0 14 EP7_IN WC 0x0 13 EP6_OUT WC 0x0 12 EP6_IN WC 0x0 11 EP5_OUT WC 0x0 10 EP5_IN WC 0x0 9 EP4_OUT WC 0x0 8 EP4_IN WC 0x0 7 EP3_OUT WC 0x0 6 EP3_IN WC 0x0 5 EP2_OUT WC 0x0 4 EP2_IN WC 0x0 3 EP1_OUT WC 0x0 2 EP1_
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RP2040 Datasheet Description Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO. Set the value of the override and then the override enable to switch over to the override value. Table 407. USB_PWR Register Bits Name Description Type Reset 31:6 Reserved.
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RP2040 Datasheet Bits Name Description Type 10 TX_DP Output data. If TX_DIFFMODE=1, Drives DPP/DPM diff pair. RW Reset 0x0 TX_DP_OE=1 to enable drive. DPP=TX_DP, DPM=~TX_DP If TX_DIFFMODE=0, Drives DPP only. TX_DP_OE=1 to enable drive. DPP=TX_DP 9 TX_DM_OE Output enable. If TX_DIFFMODE=1, Ignored. RW 0x0 RW 0x0 If TX_DIFFMODE=0, OE for DPM only. 0 - DPM in Hi-Z state; 1 - DPM driving 8 TX_DP_OE Output enable. If TX_DIFFMODE=1, OE for DPP/DPM diff pair.
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RP2040 Datasheet Bits Name 6 TX_DM_OE_OVER Description Type Reset RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RIDE_EN 5 TX_DP_OE_OVERR IDE_EN 4 DM_PULLDN_EN_ OVERRIDE_EN 3 DP_PULLDN_EN_O VERRIDE_EN 2 DP_PULLUP_EN_O VERRIDE_EN 1 DM_PULLUP_HISE L_OVERRIDE_EN 0 DP_PULLUP_HISE L_OVERRIDE_EN USBPHY_TRIM Register Description Used to adjust trim values of USB phy pull down resistors. Table 410. USBPHY_TRIM Register Bits Name Description Type Reset 31:13 Reserved.
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RP2040 Datasheet Bits Name Description Type Reset 15 DEV_RESUME_FR Set when the device receives a resume from the host. RO 0x0 OM_HOST Cleared by writing to SIE_STATUS.RESUME DEV_SUSPEND Set when the device suspend state changes. Cleared by RO 0x0 RO 0x0 14 writing to SIE_STATUS.SUSPENDED 13 DEV_CONN_DIS Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED 12 BUS_RESET Source: SIE_STATUS.BUS_RESET RO 0x0 11 VBUS_DETECT Source: SIE_STATUS.
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RP2040 Datasheet Bits Name Description Type Reset 15 DEV_RESUME_FR Set when the device receives a resume from the host. RW 0x0 OM_HOST Cleared by writing to SIE_STATUS.RESUME DEV_SUSPEND Set when the device suspend state changes. Cleared by RW 0x0 RW 0x0 14 writing to SIE_STATUS.SUSPENDED 13 DEV_CONN_DIS Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED 12 BUS_RESET Source: SIE_STATUS.BUS_RESET RW 0x0 11 VBUS_DETECT Source: SIE_STATUS.
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RP2040 Datasheet Bits Name Description Type Reset 15 DEV_RESUME_FR Set when the device receives a resume from the host. RW 0x0 OM_HOST Cleared by writing to SIE_STATUS.RESUME DEV_SUSPEND Set when the device suspend state changes. Cleared by RW 0x0 RW 0x0 14 writing to SIE_STATUS.SUSPENDED 13 DEV_CONN_DIS Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED 12 BUS_RESET Source: SIE_STATUS.BUS_RESET RW 0x0 11 VBUS_DETECT Source: SIE_STATUS.
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RP2040 Datasheet Bits Name Description Type Reset 15 DEV_RESUME_FR Set when the device receives a resume from the host. RO 0x0 OM_HOST Cleared by writing to SIE_STATUS.RESUME DEV_SUSPEND Set when the device suspend state changes. Cleared by RO 0x0 RO 0x0 14 writing to SIE_STATUS.SUSPENDED 13 DEV_CONN_DIS Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED 12 BUS_RESET Source: SIE_STATUS.BUS_RESET RO 0x0 11 VBUS_DETECT Source: SIE_STATUS.
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RP2040 Datasheet Figure 55. DMA Architecture Overview. The read master can read data from some address every clock cycle. Likewise, the write master can write to another address. The address generator produces matched pairs of read and write addresses, which the masters consume through the address FIFOs. Up to 12 transfer sequences may be in progress The DMA can perform one read access and one write access, up to 32 bits in size, every clock cycle.
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RP2040 Datasheet transfer. For example: • If the address does not increment (e.g. it is the address of a peripheral FIFO), and the next transfer sequence is to/from that same address, there is no need to write to the register again. • When transferring to/from a consecutive series of buffers in memory (e.g. scattering and gathering), an address register will already have incremented to the start of the next buffer at the completion of a transfer.
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RP2040 Datasheet 4.2.2. Starting Channels There are three ways to start a channel: • Writing to a channel trigger register • A chain trigger from another channel which has just completed, and has its CHAIN_TO field configured • The MULTI_CHAN_TRIGGER register, which can start multiple channels at once Each of these covers different use cases.
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RP2040 Datasheet • The value 0 is written to the trigger register. (This is useful for ending control block chains. See null triggers, Section 4.2.2.3) 4.2.2.2. Chaining When a channel completes, it can name a different channel to immediately be triggered. This can be used as a callback for the second channel to reconfigure and restart the first. This feature is configured through the CHAIN_TO field in the channel CTRL register. This 4-bit value selects a a channel that will start when this one finishes.
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RP2040 Datasheet 4.2.3.1. System DREQ Table There is a global assignment of DREQ numbers to peripheral DREQ channels. Table 416.
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RP2040 Datasheet and peripheral to become desynchronised, and can cause corruption or loss of data. Another caveat is that multiple channels should not be connected to the same DREQ. 4.2.4. Interrupts Each channel can generate interrupts; these can be masked on a per-channel basis using the INTE0 or INTE1 registers. There are two circumstances where a channel raises an interrupt request: • On the completion of each transfer sequence, if CTRL.IRQ_QUIET is disabled • On receiving a null trigger, if CTRL.
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RP2040 Datasheet • Bit reversal • Byte swap These manipulations do not affect the CRC calculation, just how the data is presented in the result register. 4.2.5.3. Channel Abort It is possible for a channel to get into an irrecoverable state: e.g. if commanded to transfer more data than a peripheral will ever request, it will never complete. Clearing the CTRL.EN bit merely pauses the channel, and does not solve the problem.
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RP2040 Datasheet Offset Name Info 0x024 CH0_AL2_TRANS_COUNT Alias for channel 0 TRANS_COUNT register 0x028 CH0_AL2_READ_ADDR Alias for channel 0 READ_ADDR register 0x02c CH0_AL2_WRITE_ADDR_TRIG Alias for channel 0 WRITE_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel.
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RP2040 Datasheet Offset Name Info 0x098 CH2_AL1_WRITE_ADDR Alias for channel 2 WRITE_ADDR register 0x09c CH2_AL1_TRANS_COUNT_TRIG Alias for channel 2 TRANS_COUNT register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel.
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RP2040 Datasheet Offset Name Info 0x108 CH4_TRANS_COUNT DMA Channel 4 Transfer Count 0x10c CH4_CTRL_TRIG DMA Channel 4 Control and Status 0x110 CH4_AL1_CTRL Alias for channel 4 CTRL register 0x114 CH4_AL1_READ_ADDR Alias for channel 4 READ_ADDR register 0x118 CH4_AL1_WRITE_ADDR Alias for channel 4 WRITE_ADDR register 0x11c CH4_AL1_TRANS_COUNT_TRIG Alias for channel 4 TRANS_COUNT register This is a trigger register (0xc).
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RP2040 Datasheet Offset Name Info 0x17c CH5_AL3_READ_ADDR_TRIG Alias for channel 5 READ_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel.
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RP2040 Datasheet Offset Name Info 0x1ec CH7_AL2_WRITE_ADDR_TRIG Alias for channel 7 WRITE_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel.
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RP2040 Datasheet Offset Name Info 0x25c CH9_AL1_TRANS_COUNT_TRIG Alias for channel 9 TRANS_COUNT register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel.
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RP2040 Datasheet Offset Name Info 0x2cc CH11_CTRL_TRIG DMA Channel 11 Control and Status 0x2d0 CH11_AL1_CTRL Alias for channel 11 CTRL register 0x2d4 CH11_AL1_READ_ADDR Alias for channel 11 READ_ADDR register 0x2d8 CH11_AL1_WRITE_ADDR Alias for channel 11 WRITE_ADDR register 0x2dc CH11_AL1_TRANS_COUNT_TRIG Alias for channel 11 TRANS_COUNT register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel.
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RP2040 Datasheet Offset Name 0x448 N_CHANNELS 0x800 CH0_DBG_CTDREQ 0x804 CH0_DBG_TCR Info Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer 0x840 CH1_DBG_CTDREQ 0x844 CH1_DBG_TCR Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer 0x880 CH2_DBG_CTDREQ 0x884 CH2_DBG_TCR Read to get channel TRANS_COUNT reload value, i.e.
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RP2040 Datasheet Description DMA Channel N Read Address pointer Table 418. CH0_READ_ADDR, CH1_READ_ADDR, …, CH10_READ_ADDR, Bits Name Description Type Reset 31:0 NONAME This register updates automatically each time a read RW 0x00000000 CH11_READ_ADDR completes. The current value is the next address to be read Registers by this channel. CH0_WRITE_ADDR, CH1_WRITE_ADDR, CH11_WRITE_ADDR Registers …, CH10_WRITE_ADDR, Description DMA Channel N Write Address pointer Table 419.
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RP2040 Datasheet Table 421. CH0_CTRL_TRIG, CH1_CTRL_TRIG, …, CH10_CTRL_TRIG, Bits Name Description Type Reset 31 AHB_ERROR Logical OR of the READ_ERROR and WRITE_ERROR flags. RO 0x0 WC 0x0 WC 0x0 CH11_CTRL_TRIG The channel halts when it encounters any bus error, and Registers always raises its channel IRQ flag. 30 READ_ERROR If 1, the channel received a read bus error. Write one to clear.
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RP2040 Datasheet Bits Name Description Type Reset 20:15 TREQ_SEL Select a Transfer Request signal. RW 0x00 RW varies RW 0x0 Size of address wrap region. If 0, don’t wrap. For values n > RW 0x0 The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).
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RP2040 Datasheet Bits Name Description Type Reset 1 HIGH_PRIORITY HIGH_PRIORITY gives a channel preferential treatment in RW 0x0 RW 0x0 issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA’s bus priority is not changed.
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RP2040 Datasheet Table 425. CH0_AL1_TRANS_COU NT_TRIG, CH1_AL1_TRANS_COU Bits Name 31:0 NONAME Description Type Reset RO - NT_TRIG, …, CH10_AL1_TRANS_CO UNT_TRIG, CH11_AL1_TRANS_CO UNT_TRIG Registers CH0_AL2_CTRL, Registers CH1_AL2_CTRL, …, CH10_AL2_CTRL, CH11_AL2_CTRL Description Alias for channel N CTRL register Table 426.
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RP2040 Datasheet Table 430. CH0_AL3_CTRL, CH1_AL3_CTRL, …, CH10_AL3_CTRL, Bits Name 31:0 NONAME Description Type Reset RO - CH11_AL3_CTRL Registers CH0_AL3_WRITE_ADDR, CH1_AL3_WRITE_ADDR, …, CH10_AL3_WRITE_ADDR, CH11_AL3_WRITE_ADDR Registers Description Alias for channel N WRITE_ADDR register Table 431.
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RP2040 Datasheet Table 434. INTR Register Bits Name Description Type Reset 31:16 Reserved. - - - 15:0 NONAME Raw interrupt status for DMA Channels 0..15. Bit n RO 0x0000 corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR, INTS0 or INTS1. Channel interrupts can be routed to either of two systemlevel IRQs based on INTE0 and INTE1.
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RP2040 Datasheet Table 437. INTS0 Register Bits Name Description Type Reset 31:16 Reserved. - - - 15:0 NONAME Indicates active channel interrupt requests which are WC 0x0000 currently causing IRQ 0 to be asserted. Channel interrupts can be cleared by writing a bit mask here. INTE1 Register Description Interrupt Enables for IRQ 1 Table 438. INTE1 Register Bits Name Description Type Reset 31:16 Reserved. - - - 15:0 NONAME Set bit n to pass interrupts from channel n to DMA IRQ 1.
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RP2040 Datasheet Table 441. TIMER0, TIMER1 Registers Bits Name Description Type Reset 31:16 X Pacing Timer Dividend. Specifies the X value for the (X/Y) RW 0x0000 RW 0x0000 fractional timer. 15:0 Y Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. MULTI_CHAN_TRIGGER Register Description Trigger one or more channels simultaneously Table 442. MULTI_CHAN_TRIGGE R Register Bits Name Description Type Reset 31:16 Reserved.
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RP2040 Datasheet Bits Name Description Type Reset 0 EN Enable sniffer RW 0x0 SNIFF_DATA Register Description Data accumulator for sniff hardware Table 444. SNIFF_DATA Register Bits Name Description Type Reset 31:0 NONAME Write an initial seed value here before starting a DMA RW 0x00000000 transfer on the channel indicated by SNIFF_CTRL_DMACH. The hardware will update this register each time it observes a read from the indicated channel.
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RP2040 Datasheet Table 447. N_CHANNELS Register Bits Name Description Type Reset 31:5 Reserved. - - - 4:0 NONAME The number of channels this DMA instance is equipped RO - with. This DMA supports up to 16 hardware channels, but can be configured with as few as one, to minimise silicon area. CH0_DBG_CTDREQ, CH1_DBG_CTDREQ, CH11_DBG_CTDREQ Registers Table 448.
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RP2040 Datasheet • Received data rx (referred to as UARTRXD in the following sections) • Output flow control rts (referred to as nUARTRTS in the following sections) • Input flow control cts (referred to as nUARTCTS in the following sections) The modem mode and IrDA mode of the PL011 are not supported. The UARTCLK is driven from clk_peri, and PCLK is driven from the system clock clk_sys (see Figure 26). 4.3.1.
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RP2040 Datasheet Figure 57. UART block diagram. Test logic is not shown for clarity. 4.3.2.1. AMBA APB interface The AMBA APB interface generates read and write decodes for accesses to status/control registers, and the transmit and receive FIFOs. 4.3.2.2. Register block The register block stores data written, or to be read across the AMBA APB interface. 4.3.2.3. Baud rate generator The baud rate generator contains free-running counters that generate the internal clocks: Baud16 and IrLPBaud16 signals.
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RP2040 Datasheet 4.3.2.6. Transmit logic The transmit logic performs parallel-to-serial conversion on the data read from the transmit FIFO. Control logic outputs the serial bit stream beginning with a start bit, data bits with the Least Significant Bit (LSB) first, followed by the parity bit, and then the stop bits according to the programmed configuration in control registers. 4.3.2.7.
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RP2040 Datasheet 4.3.3.2. UART operation Control data is written to the UART Line Control Register, UARTLCR. This register is 30-bits wide internally, but is externally accessed through the APB interface by writes to the following registers: The UARTLCR_H register defines the: • transmission parameters • word length • buffer mode • number of transmitted stop bits • parity mode • break generation.
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RP2040 Datasheet pulses (half way through a bit period). The start bit is valid if UARTRXD is still LOW on the eighth cycle of Baud16, otherwise a false start bit is detected and it is ignored. If the start bit was valid, successive data bits are sampled on every 16th cycle of Baud16 (that is, one bit period later) according to the programmed length of the data characters. The parity bit is then checked if parity mode was enabled.
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RP2040 Datasheet Figure 59. UART Data bits Start bit character frame. TXD 0 1 0 1 0 Stop bit 0 1 1 0 1 DMASREQ Bit period 3/16 Bit period 1 0 DMABREQ DMACLR 0 1 0 1 0 Start 0 Data bits 1 1 Stop 4.3.4. UART hardware flow control The hardware flow control feature is fully selectable, and enables you to control the serial data flow by using the nUARTRTS output and nUARTCTS input signals. Figure 60 shows how two devices can communicate with each other using hardware flow control.
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RP2040 Datasheet The nUARTRTS signal is reasserted when data has been read out of the receive FIFO so that it is filled to less than the watermark level. If RTS flow control is disabled and the UART is still enabled, then data is received until the receive FIFO is full, or no more data is transmitted to it. 4.3.4.2. CTS flow control If CTS flow control is enabled, then the transmitter checks the nUARTCTS signal before transmitting the next byte.
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RP2040 Datasheet  NOTE For the remaining three characters the UART cannot assert the burst request. Each request signal remains asserted until the relevant DMACLR signal is asserted. After the request clear signal is deasserted, a request signal can become active again, depending on the conditions described previously. All request signals are deasserted if the UART is disabled or the relevant DMA enable bit, TXDMAE or RXDMAE, in the DMA Control Register, UARTDMACR, is cleared.
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RP2040 Datasheet FIFO trigger levels. The error interrupt, UARTEINTR, can be triggered when there is an error in the reception of data. A number of error conditions are possible. The modem status interrupt, UARTMSINTR, is a combined interrupt of all the individual modem status signals. The status of the individual interrupt sources can be read either from the Raw Interrupt Status Register, UARTRIS, or from the Masked Interrupt Status Register, UARTMIS. 4.3.6.1.
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RP2040 Datasheet 4.3.6.5. UARTEINTR The error interrupt is asserted when an error occurs in the reception of data by the UART. The interrupt can be caused by a number of different error conditions: • framing • parity • break • overrun. You can determine the cause of the interrupt by reading the Raw Interrupt Status Register, UARTRIS, or the Masked Interrupt Status Register, UARTMIS.
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RP2040 Datasheet 48 49 uart_reset(uart); 50 uart_unreset(uart); 51 52 // FIXME clk_peri enable mask needs to be set.
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RP2040 Datasheet 97 } 4.3.8. List of Registers Table 453.
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RP2040 Datasheet Bits Name Description Type Reset 10 BE Break error. This bit is set to 1 if a break condition was RO - Parity error. When set to 1, it indicates that the parity of the RO - detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity and stop bits). In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO.
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RP2040 Datasheet Bits Name Description Type Reset 0 FE Framing error. When set to 1, it indicates that the received WC 0x0 character did not have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. UARTFR Register Description Flag Register, UARTFR Table 456. UARTFR Register Bits Name Description Type Reset 31:9 Reserved. - - - 8 RI Ring indicator.
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RP2040 Datasheet Bits Name Description Type Reset 1 DSR Data set ready. This bit is the complement of the UART RO - Clear to send. This bit is the complement of the UART clear RO - data set ready, nUARTDSR, modem status input. That is, the bit is 1 when nUARTDSR is LOW. 0 CTS to send, nUARTCTS, modem status input. That is, the bit is 1 when nUARTCTS is LOW. UARTILPR Register Description IrDA Low-Power Counter Register, UARTILPR Table 457.
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RP2040 Datasheet Bits Name Description Type Reset 6:5 WLEN Word length. These bits indicate the number of data bits RW 0x0 Enable FIFOs: 0 = FIFOs are disabled (character mode) that RW 0x0 transmitted or received in a frame as follows: b11 = 8 bits b10 = 7 bits b01 = 6 bits b00 = 5 bits. 4 FEN is, the FIFOs become 1-byte-deep holding registers 1 = transmit and receive FIFO buffers are enabled (FIFO mode). 3 STP2 Two stop bits select.
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RP2040 Datasheet Bits Name Description Type Reset 11 RTS Request to send. This bit is the complement of the UART RW 0x0 RW 0x0 RW 0x1 RW 0x1 RW 0x0 request to send, nUARTRTS, modem status output. That is, when the bit is programmed to a 1 then nUARTRTS is LOW. 10 DTR Data transmit ready. This bit is the complement of the UART data transmit ready, nUARTDTR, modem status output. That is, when the bit is programmed to a 1 then nUARTDTR is LOW. 9 RXE Receive enable.
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RP2040 Datasheet Bits Name Description Type Reset 1 SIREN SIR enable: 0 = IrDA SIR ENDEC is disabled. nSIROUT RW 0x0 RW 0x0 remains LOW (no light pulse generated), and signal transitions on SIRIN have no effect. 1 = IrDA SIR ENDEC is enabled. Data is transmitted and received on nSIROUT and SIRIN. UARTTXD remains HIGH, in the marking state. Signal transitions on UARTRXD or modem status inputs have no effect. This bit has no effect if the UARTEN bit disables the UART.
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RP2040 Datasheet Bits Name Description Type 8 PEIM Parity error interrupt mask. A read returns the current mask RW Reset 0x0 for the UARTPEINTR interrupt. On a write of 1, the mask of the UARTPEINTR interrupt is set. A write of 0 clears the mask. 7 FEIM Framing error interrupt mask. A read returns the current RW 0x0 RW 0x0 RW 0x0 Receive interrupt mask. A read returns the current mask for RW 0x0 mask for the UARTFEINTR interrupt.
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RP2040 Datasheet Bits Name Description Type 8 PERIS Parity error interrupt status. Returns the raw interrupt state RO Reset 0x0 of the UARTPEINTR interrupt. 7 FERIS Framing error interrupt status. Returns the raw interrupt RO 0x0 RO 0x0 Transmit interrupt status. Returns the raw interrupt state of RO 0x0 state of the UARTFEINTR interrupt. 6 RTRIS Receive timeout interrupt status. Returns the raw interrupt state of the UARTRTINTR interrupt. a 5 TXRIS the UARTTXINTR interrupt.
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RP2040 Datasheet Bits Name Description Type Reset 1 CTSMMIS nUARTCTS modem masked interrupt status. Returns the RO - RO - masked interrupt state of the UARTCTSINTR interrupt. 0 RIMMIS nUARTRI modem masked interrupt status. Returns the masked interrupt state of the UARTRIINTR interrupt. UARTICR Register Description Interrupt Clear Register, UARTICR Table 466. UARTICR Register Bits Name Description Type Reset 31:11 Reserved. - - - 10 OEIC Overrun error interrupt clear.
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RP2040 Datasheet Bits Name Description Type Reset 0 RXDMAE Receive DMA enable. If this bit is set to 1, DMA for the RW 0x0 receive FIFO is enabled. UARTPERIPHID0 Register Description UARTPeriphID0 Register Table 468. UARTPERIPHID0 Register Bits Name Description Type Reset 31:8 Reserved. - - - 7:0 PARTNUMBER0 These bits read back as 0x11 RO 0x11 UARTPERIPHID1 Register Description UARTPeriphID1 Register Table 469.
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RP2040 Datasheet Table 472. UARTPCELLID0 Register Bits Name Description Type Reset 31:8 Reserved. - - - 7:0 UARTPCELLID0 These bits read back as 0x0D RO 0x0d UARTPCELLID1 Register Description UARTPCellID1 Register Table 473. UARTPCELLID1 Register Bits Name Description Type Reset 31:8 Reserved. - - - 7:0 UARTPCELLID1 These bits read back as 0xF0 RO 0xf0 UARTPCELLID2 Register Description UARTPCellID2 Register Table 474.
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RP2040 Datasheet • Master or Slave (Default to Master mode) • Standard mode, Fast mode or Fast mode plus • Default slave address 0x055 • Supports 10-bit addressing in Master mode • 16-element transmit buffer • 16-element receive buffer • Can be driven from DMA • Can generate interrupts 4.4.1.1. Standard The I2C controller was designed for I2C Bus specification, version 6.0, dated April 2014. 4.4.1.2. Clocking The I2C controller is connected to clk_sys.
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RP2040 Datasheet • Allows restart conditions when a master (can be disabled for legacy device support) • Configurable timing to adjust TsuDAT/ThDAT • General calls responded to on reset • Interface to DMA • Single interrupt output • Configurable timing to adjust clock frequency • Spike suppression (default 7 clk_sys cycles) • Can NACK after data received by Slave • Hold transfer when TX FIFO empty • Hold bus until space available in RX FIFO • Restart detect interrupt in Slave mode • Optional blocking Maste
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RP2040 Datasheet bus and every device can talk with any master, passing information back and forth. There needs to be at least one master (such as a microcontroller or DSP) on the bus but there can be multiple masters, which require them to arbitrate for ownership. Multiple masters and arbitration are explained later in this chapter. The I2C block does not support SMBus and PMBus protocols (for System Management and Power management).
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RP2040 Datasheet 4.4.4. I2C Terminology The following terms are used and are defined as follows: 4.4.4.1. I2C Bus Terms The following terms relate to how the role of the I2C device and how it interacts with other I2C devices on the bus. • Transmitter – the device that sends data to the bus. A transmitter can either be a device that initiates the data transmission to the bus (a master-transmitter) or responds to a request from the master to send data to the bus (a slave-transmitter).
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RP2040 Datasheet Each slave has a unique address that is determined by the system designer. When a master wants to communicate with a slave, the master transmits a START/RESTART condition that is then followed by the slave’s address and a control bit (R/W) to determine if the master wants to transmit data or receive data from the slave. The slave then sends an acknowledge (ACK) pulse after the address.
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RP2040 Datasheet 4.4.6.1. START and STOP Conditions When the bus is idle, both the SCL and SDA signals are pulled high through external pull-up resistors on the bus. When the master wants to start a transmission on the bus, the master issues a START condition. This is defined to be a high-to-low transition of the SDA signal while SCL is 1. When the master wants to terminate the transmission, the master issues a STOP condition. This is defined to be a low-to-high transition of the SDA line while SCL is 1.
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RP2040 Datasheet Table 476. I2C/SMBus Definition of Bits in First Byte Slave Address R/W Bit 0000 000 Description 0 General Call Address. DW_apb_i2c places the data in the receive buffer and issues a General Call interrupt. 0000 000 1 START byte. For more details, refer to Section 4.4.6.4. 0000 001 X CBUS address. DW_apb_i2c ignores these accesses. 0000 010 X Reserved. 0000 011 X Reserved. 0000 1XX X High-speed master code (for more information, refer to Section 4.4.8).
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RP2040 Datasheet 4.4.6.3.2. Master-Receiver and Slave-Transmitter If the master is receiving data as shown in Figure 68, then the master responds to the slave-transmitter with an acknowledge pulse after a byte of data has been received, except for the last byte. This is the way the master-receiver notifies the slave-transmitter that this is the last byte. The slave-transmitter relinquishes the SDA line after detecting the No Acknowledge (NACK) so that the master can issue a STOP condition. Figure 68.
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RP2040 Datasheet 5. Master generates a RESTART (R) condition. A hardware receiver does not respond to the START BYTE because it is a reserved address and resets after the RESTART condition is generated. 4.4.7. Tx FIFO Management and START, STOP and RESTART Generation When operating as a master, the DW_apb_i2c component supports the mode of Tx FIFO management illustrated in Figure 70 4.4.7.1.
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RP2040 Datasheet Figure 73.
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RP2040 Datasheet Figure 78.
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RP2040 Datasheet clock. Clock synchronization is performed using the wired-AND connection to the SCL signal. When the master transitions the SCL clock to zero, the master starts counting the low time of the SCL clock and transitions the SCL clock signal to one at the beginning of the next clock period. However, if another master is holding the SCL line to 0, then the master goes into a HIGH wait state until the SCL clock line transitions to one.
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RP2040 Datasheet  NOTE Slaves and masters do not have to be programmed with the same type of addressing 7-bit or 10-bit address. For instance, a slave can be programmed with 7-bit addressing and a master with 10-bit addressing, and vice versa. 1. Enable the DW_apb_i2c by writing a ‘1’ to IC_ENABLE.ENABLE.  NOTE Depending on the reset values chosen, steps two and three may not be necessary because the reset values can be configured.
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RP2040 Datasheet  NOTE The value of 10 is recommended here because this is approximately the amount of time required for a single byte of data transferred on the I2C bus. 1. If there is any data remaining in the Tx FIFO before receiving the read request, then the DW_apb_i2c asserts a TX_ABRT interrupt (bit six of the IC_RAW_INTR_STAT register) to flush the old data from the TX FIFO. If the TX_ABRT interrupt has been masked, due to IC_INTR_MASK.
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RP2040 Datasheet  NOTE If the Rx FIFO is completely filled with data when a byte is pushed, then the DW_apb_i2c slave holds the I2C SCL line low until the Rx FIFO has some space, and then continues with the next read request. 1. DW_apb_i2c asserts the RX_FULL interrupt IC_RAW_INTR_STAT.RX_FULL. If the RX_FULL interrupt has been masked, due to setting IC_INTR_MASK.
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RP2040 Datasheet 4.4.10.2.1. Initial Configuration To use the DW_apb_i2c as a master perform the following steps: 1. Disable the DW_apb_i2c by writing zero to IC_ENABLE.ENABLE. 2. Write to the IC_CON register to set the maximum speed mode supported (bits 2:1) and the desired speed of the DW_apb_i2c master-initiated transfers, either 7-bit or 10-bit addressing (bit 4). Ensure that bit six (IC_SLAVE_DISABLE) is written with a ‘1’ and bit zero (MASTER_MODE) is written with a ‘1’.
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RP2040 Datasheet  NOTE The DW_apb_i2c Master can be disabled only if the current command being processed—when the ic_enable deassertion occurs—has the STOP bit set to one. When an attempt is made to disable the DW_apb_i2c Master while processing a command without the STOP bit set, the DW_apb_i2c Master continues to remain active, holding the SCL line low until a new command is received in the Tx FIFO.
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RP2040 Datasheet they remain stable for a predetermined amount of ic_clk cycles before they are sampled internally. There is one separate counter for each signal (SCL and SDA). The number of ic_clk cycles can be programmed by the user and should be calculated taking into account the frequency of ic_clk and the relevant spike length specification. Each counter is started whenever its input signal changes its value.
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RP2040 Datasheet  NOTE • Because the minimum value that can be programmed into the IC_FS_SPKLEN register is one, the spike length specification can be exceeded for low frequencies of ic_clk. Consider the simple example of a 10 MHz (100 ns period) ic_clk; in this case, the minimum spike length that can be programmed is 100 ns, which means that spikes up to this length are suppressed.
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RP2040 Datasheet Figure 82. SDA Recovery with 9 SCL 0 Recovery Clocks Clocks 1 2 3 4 5 6 7 8 9 10 SCL SDA Master drives 9 clocks to recover SDA stuck at low MST_SDA Figure 83. SDA Recovery with 6 SCL Recovery Clocks Clocks 0 1 2 3 4 5 6 7 SCL SDA MST_SDA Master drives 9 clocks to recover SDA stuck at low 4.4.13.2.
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RP2040 Datasheet Timing Parameter Symbol Standard Speed Fast Speed / Fast Speed Plus Bus free time between a tBUF IC_SS_SCL_LCNT IC_FS_SCL_LCNT Spike length tSP IC_FS_SPKLEN IC_FS_SPKLEN Data hold time tHD;DAT IC_SDA_HOLD IC_SDA_HOLD Data setup time tSU;DAT IC_SDA_SETUP IC_SDA_SETUP STOP and a START condition 4.4.14.1. Minimum High and Low Counts in SS, FS, and FM+ Modes.
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RP2040 Datasheet Figure 84. Impact of SCL Rise Time and Fall Time on ic_clk Generated SCL ic_clk_in_a/SCL HCNT + IC_*_SPKLEN + 7 SCL rise time LCNT + 1 SCL fall time SCL rise time SCL_High_time = [(HCNT + IC_*_SPKLEN + 7) * ic_clk] + SCL_Fall_time SCL_low_time = [(LCNT + 1) * ic_clk] - SCL_Fall_time + SCL_Rise_time 4.4.14.2. Minimum IC_CLK Frequency This section describes the minimum ic_clk frequencies that the DW_apb_i2c supports for each speed mode, and the associated high and low count values.
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RP2040 Datasheet IC_LCNT_FS × (2.5μs / (IC_LCNT_FS + 14) ) = 1.3μs The previous equation gives: IC_LCNT_FS = roundup(15.166) = 16 These calculations produce IC_LCNT_FS = 16 and IC_HCNT_FS = 14, giving an ic_clk value of: 2.5 μs / (16 + 14) = 83.3ns = 12MHz Testing these results shows that protocol requirements are satisfied. Table 478 lists the minimum ic_clk values for all modes with high and low count values. Table 478.
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RP2040 Datasheet MIN_SCL_LOWtime = Minimum Low Period MIN_SCL_LOWtime = 4700 ns for 100 kbps, 1300 ns for 400 kbps, 500 ns for 1000 kbps, 160 ns for 3.4Mbs, bus loading = 100pF 320 ns for 3.4Mbs, bus loading = 400pF OSCFREQ = ic_clk Clock Frequency (Hz). For example: OSCFREQ = 100 MHz I2Cmode = fast, 400 kbit/s MIN_SCL_HIGHtime = 600 ns. MIN_SCL_LOWtime = 1300 ns.
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RP2040 Datasheet 4.4.15.3. Watermark Levels In DW_apb_i2c the registers for setting watermarks to allow DMA bursts do not need be set to anything other than their reset value. Specifically IC_DMA_TDLR and IC_DMA_RDLR can be left at reset values of zero. This is because only single transfers are needed due to the low bandwidth of I2C relative to system bandwidth, and also the DMA controller normally has highest priority on the system bus so will generally complete very quickly. 4.4.15.4.
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RP2040 Datasheet Offset Name Info 0x34 IC_RAW_INTR_STAT I2C Raw Interrupt Status Register 0x38 IC_RX_TL I2C Receive FIFO Threshold Register 0x3c IC_TX_TL I2C Transmit FIFO Threshold Register 0x40 IC_CLR_INTR Clear Combined and Individual Interrupt Register 0x44 IC_CLR_RX_UNDER Clear RX_UNDER Interrupt Register 0x48 IC_CLR_RX_OVER Clear RX_OVER Interrupt Register 0x4c IC_CLR_TX_OVER Clear TX_OVER Interrupt Register 0x50 IC_CLR_RD_REQ Clear RD_REQ Interrupt Register 0x54 IC_CLR_TX
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RP2040 Datasheet Read/Write Access: - bit 10 is read only. - bit 11 is read only - bit 16 is read only - bit 17 is read only - bits 18 and 19 are read only. Table 481. IC_CON Register Bits Name Description Type Reset 31:11 Reserved.
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RP2040 Datasheet Bits Name Description Type Reset 5 IC_RESTART_EN Determines whether RESTART conditions may be sent RW 0x1 RW 0x0 RW 0x0 when acting as a master. Some older slaves do not support handling RESTART conditions; however, RESTART conditions are used in several DW_apb_i2c operations.
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RP2040 Datasheet Bits Name Description Type Reset 2:1 SPEED These bits control at which speed the DW_apb_i2c RW 0x2 RW 0x1 operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode.
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RP2040 Datasheet Bits Name Description Type 11 SPECIAL This bit indicates whether software performs a Device-ID or RW Reset 0x0 General Call or START BYTE command.
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RP2040 Datasheet Table 483. IC_SAR Register Bits Name Description Type Reset 31:10 Reserved. - - - 9:0 IC_SAR The IC_SAR holds the slave address when the I2C is RW 0x055 operating as a slave. For 7-bit addressing, only IC_SAR[6:0] is used. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.
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RP2040 Datasheet Bits Name Description Type Reset 10 RESTART This bit controls whether a RESTART is issued before the SC 0x0 SC 0x0 byte is sent or received. 1 - If IC_RESTART_EN is 1, a RESTART is issued before the data is sent/received (according to the value of CMD), regardless of whether or not the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead.
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RP2040 Datasheet Bits Name Description Type Reset 8 CMD This bit controls whether a read or a write is performed. SC 0x0 RW 0x00 This bit does not control the direction when the DW_apb_i2con acts as a slave. It controls only the direction when it acts as a master. When a command is entered in the TX FIFO, this bit distinguishes the write and read commands. In slavereceiver mode, this bit is a 'don’t care' because writes to this register are not required.
PAGE 497
RP2040 Datasheet Table 485. IC_SS_SCL_HCNT Register Bits Name Description Type Reset 31:16 Reserved. - - - 15:0 IC_SS_SCL_HCNT This register must be set before any I2C bus transaction RW 0x0028 can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration'.
PAGE 498
RP2040 Datasheet Table 487. IC_FS_SCL_HCNT Register Bits Name Description Type Reset 31:16 Reserved. - - - 15:0 IC_FS_SCL_HCNT This register must be set before any I2C bus transaction RW 0x0006 can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for fast mode or fast mode plus. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'.
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RP2040 Datasheet Table 488. IC_FS_SCL_LCNT Register Bits Name Description Type Reset 31:16 Reserved. - - - 15:0 IC_FS_SCL_LCNT This register must be set before any I2C bus transaction RW 0x000d can take place to ensure proper I/O timing. This register sets the SCL clock low period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'.
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RP2040 Datasheet Bits Name Description Type Reset 11 R_GEN_CALL See IC_RAW_INTR_STAT for a detailed description of RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 R_GEN_CALL bit. Reset value: 0x0 0x0 -> R_GEN_CALL interrupt is inactive 0x1 -> R_GEN_CALL interrupt is active 10 R_START_DET See IC_RAW_INTR_STAT for a detailed description of R_START_DET bit.
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RP2040 Datasheet Bits Name Description Type Reset 3 R_TX_OVER See IC_RAW_INTR_STAT for a detailed description of RO 0x0 RO 0x0 RO 0x0 RO 0x0 R_TX_OVER bit. Reset value: 0x0 0x0 -> R_TX_OVER interrupt is inactive 0x1 -> R_TX_OVER interrupt is active 2 R_RX_FULL See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL bit.
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RP2040 Datasheet Bits Name Description Type 11 M_GEN_CALL This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT RW Reset 0x1 register. Reset value: 0x1 0x0 -> GEN_CALL interrupt is masked 0x1 -> GEN_CALL interrupt is unmasked 10 M_START_DET This bit masks the R_START_DET interrupt in RW 0x0 This bit masks the R_STOP_DET interrupt in IC_INTR_STAT RW 0x0 IC_INTR_STAT register.
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RP2040 Datasheet Bits Name Description Type Reset 3 M_TX_OVER This bit masks the R_TX_OVER interrupt in IC_INTR_STAT RW 0x1 RW 0x1 RW 0x1 This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT RW 0x1 register. Reset value: 0x1 0x0 -> TX_OVER interrupt is masked 0x1 -> TX_OVER interrupt is unmasked 2 M_RX_FULL This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register.
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RP2040 Datasheet Bits Name Description Type Reset 12 RESTART_DET Indicates whether a RESTART condition has occurred on RO 0x0 RO 0x0 RO 0x0 the I2C interface when DW_apb_i2c is operating in Slave mode and the slave is being addressed. Enabled only when IC_SLV_RESTART_DET_EN=1. Note: However, in high-speed mode or during a START BYTE transfer, the RESTART comes before the address field as per the I2C protocol.
PAGE 505
RP2040 Datasheet Bits Name Description Type Reset 9 STOP_DET Indicates whether a STOP condition has occurred on the RO 0x0 RO 0x0 RO 0x0 I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. In Slave Mode: - If IC_CON[7]=1’b1 (STOP_DET_IFADDRESSED), the STOP_DET interrupt will be issued only if slave is addressed.
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RP2040 Datasheet Bits Name Description Type Reset 6 TX_ABRT This bit indicates if DW_apb_i2c, as an I2C transmitter, is RO 0x0 RO 0x0 RO 0x0 unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a 'transmit abort'. When this bit is set to 1, the IC_TX_ABRT_SOURCE register indicates the reason why the transmit abort takes places.
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RP2040 Datasheet Bits Name Description Type Reset 3 TX_OVER Set during transmit if the transmit buffer is filled to RO 0x0 RO 0x0 RO 0x0 RO 0x0 IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. When the module is disabled, this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared.
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RP2040 Datasheet Description I2C Receive FIFO Threshold Register Table 492. IC_RX_TL Register Bits Name Description Type Reset 31:8 Reserved. - - - 7:0 RX_TL Receive FIFO Threshold Level. RW 0x00 Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that hardware does not allow this value to be set to a value larger than the depth of the buffer.
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RP2040 Datasheet Table 494. IC_CLR_INTR Register Bits Name Description Type Reset 31:1 Reserved. - - - 0 CLR_INTR Read this register to clear the combined interrupt, all RO 0x0 individual interrupts, and the IC_TX_ABRT_SOURCE register. This bit does not clear hardware clearable interrupts but software clearable interrupts. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE.
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RP2040 Datasheet Description Clear RD_REQ Interrupt Register Table 498. IC_CLR_RD_REQ Register Bits Name Description Type Reset 31:1 Reserved. - - - 0 CLR_RD_REQ Read this register to clear the RD_REQ interrupt (bit 5) of RO 0x0 the IC_RAW_INTR_STAT register. Reset value: 0x0 IC_CLR_TX_ABRT Register Description Clear TX_ABRT Interrupt Register Table 499. IC_CLR_TX_ABRT Register Bits Name Description Type Reset 31:1 Reserved.
PAGE 511
RP2040 Datasheet Table 501. IC_CLR_ACTIVITY Register Bits Name Description Type Reset 31:1 Reserved. - - - 0 CLR_ACTIVITY Reading this register clears the ACTIVITY interrupt if the RO 0x0 I2C is not active anymore. If the I2C module is still active on the bus, the ACTIVITY interrupt bit continues to be set. It is automatically cleared by hardware if the module is disabled and if there is no further activity on the bus.
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RP2040 Datasheet Description I2C Enable Register Table 505. IC_ENABLE Register Bits Name Description Type Reset 31:3 Reserved. - - - 2 TX_CMD_BLOCK In Master mode: - 1’b1: Blocks the transmission of data on RW 0x0 RW 0x0 I2C bus even if Tx FIFO has data to transmit. - 1’b0: The transmission of data starts on I2C bus automatically, as soon as the first data is available in the Tx FIFO.
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RP2040 Datasheet Bits Name Description Type Reset 0 ENABLE Controls whether the DW_apb_i2c is enabled. - 0: Disables RW 0x0 DW_apb_i2c (TX and RX FIFOs are held in an erased state) 1: Enables DW_apb_i2c Software can disable DW_apb_i2c while it is active. However, it is important that care be taken to ensure that DW_apb_i2c is disabled properly. A recommended procedure is described in 'Disabling DW_apb_i2c'. When DW_apb_i2c is disabled, the following occurs: - The TX FIFO and RX FIFO get flushed.
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RP2040 Datasheet Bits Name Description Type Reset 5 MST_ACTIVITY Master FSM Activity Status. When the Master Finite State RO 0x0 RO 0x0 RO 0x0 RO 0x1 RO 0x1 RO 0x0 Machine (FSM) is not in the IDLE state, this bit is set. - 0: Master FSM is in IDLE state so the Master part of DW_apb_i2c is not Active - 1: Master FSM is not in IDLE state so the Master part of DW_apb_i2c is Active Note: IC_STATUS[0]-that is, ACTIVITY bit-is the OR of SLV_ACTIVITY and MST_ACTIVITY bits.
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RP2040 Datasheet Table 507. IC_TXFLR Register Bits Name Description Type Reset 31:5 Reserved. - - - 4:0 TXFLR Transmit FIFO Level. Contains the number of valid data RO 0x00 entries in the transmit FIFO. Reset value: 0x0 IC_RXFLR Register Description I2C Receive FIFO Level Register This register contains the number of valid data entries in the receive FIFO buffer.
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RP2040 Datasheet IC_TX_ABRT_SOURCE Register Description I2C Transmit Abort Source Register This register has 32 bits that indicate the source of the TX_ABRT bit. Except for Bit 9, this register is cleared whenever the IC_CLR_TX_ABRT register or the IC_CLR_INTR register is read. To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; RESTART must be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]).
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RP2040 Datasheet Bits Name 14 ABRT_SLV_ARBLO This field indicates that a Slave has lost the bus while ST Description Type Reset RO 0x0 RO 0x0 This field specifies that the Master has lost arbitration, or if RO 0x0 transmitting data to a remote master. IC_TX_ABRT_SOURCE[12] is set at the same time. Note: Even though the slave never 'owns' the bus, something could go wrong on the bus. This is a fail safe check.
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RP2040 Datasheet Bits Name 10 ABRT_10B_RD_NO This field indicates that the restart is disabled RSTRT Description Type Reset RO 0x0 RO 0x0 RO 0x0 RO 0x0 (IC_RESTART_EN bit (IC_CON[5]) =0) and the master sends a read command in 10-bit addressing mode.
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RP2040 Datasheet Bits Name Description Type Reset 6 ABRT_HS_ACKDE This field indicates that the Master is in High Speed mode RO 0x0 T and the High Speed Master code was acknowledged RO 0x0 RO 0x0 RO 0x0 RO 0x0 (wrong behavior).
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RP2040 Datasheet Bits Name Description Type Reset 1 ABRT_10ADDR1_ This field indicates that the Master is in 10-bit address RO 0x0 NOACK mode and the first 10-bit address byte was not RO 0x0 acknowledged by any slave.
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RP2040 Datasheet Table 511. IC_SLV_DATA_NACK_ ONLY Register Bits Name Description Type Reset 31:1 Reserved. - - - 0 NACK Generate NACK. This NACK generation only occurs when RW 0x0 DW_apb_i2c is a slave-receiver. If this register is set to a value of 1, it can only generate a NACK after a data byte is received; hence, the data transfer is aborted and the data received is not pushed to the receive buffer.
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RP2040 Datasheet Table 513. IC_DMA_TDLR Register Bits Name Description Type Reset 31:4 Reserved. - - - 3:0 DMATDL Transmit Data Level. This bit field controls the level at RW 0x0 which a DMA request is made by the transmit logic. It is equal to the watermark level; that is, the dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO is equal to or below this field value, and TDMAE = 1.
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RP2040 Datasheet Table 515. IC_SDA_SETUP Register Bits Name Description Type Reset 31:8 Reserved. - - - 7:0 SDA_SETUP SDA Setup. It is recommended that if the required delay is RW 0x64 1000ns, then for an ic_clk frequency of 10 MHz, IC_SDA_SETUP should be programmed to a value of 11. IC_SDA_SETUP must be programmed with a minimum value of 2.
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RP2040 Datasheet Bits Name 2 SLV_RX_DATA_LO Slave Received Data Lost. This bit indicates if a SlaveST Description Type Reset RO 0x0 Receiver operation has been aborted with at least one data byte received from an I2C transfer due to the setting bit 0 of IC_ENABLE from 1 to 0.
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RP2040 Datasheet Bits Name 1 SLV_DISABLED_W Slave Disabled While Busy (Transmit, Receive). This bit HILE_BUSY Description Type Reset RO 0x0 ic_en Status. This bit always reflects the value driven on the RO 0x0 indicates if a potential or active Slave operation has been aborted due to the setting bit 0 of the IC_ENABLE register from 1 to 0.
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RP2040 Datasheet suppression logic when the component is operating in SS, FS or FM+ modes. The relevant I2C requirement is tSP (table 4) as detailed in the I2C Bus Specification. This register must be programmed with a minimum value of 1. Table 518. IC_FS_SPKLEN Register Bits Name Description Type Reset 31:8 Reserved. - - - 7:0 IC_FS_SPKLEN This register must be set before any I2C bus transaction RW 0x07 can take place to ensure stable operation.
PAGE 527
RP2040 Datasheet Bits Name Description 3:2 MAX_SPEED_MOD MAX SPEED MODE = FAST MODE Type Reset RO 0x0 RO 0x0 Type Reset RO 0x3230312a E 1:0 APB_DATA_WIDT APB data bus width is 32 bits H IC_COMP_VERSION Register Description I2C Component Version Register Table 521.
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RP2040 Datasheet Each controller can be connected to a number of GPIO pins as defined in the GPIO muxing Table 274 in Section 2.18.2.
PAGE 529
RP2040 Datasheet Figure 85. PrimeCell SSPTXINTR SSP block diagram. For clarity, does not show the test logic.
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RP2040 Datasheet When configured as a master or slave, serial data received through the SSPRXD pin is registered prior to parallel loading into the attached slave or master receive FIFO respectively. 4.5.2.6. Transmit and receive logic When configured as a master, the clock to the attached slaves is derived from a divided-down version of SSPCLK through the previously described prescaler operations.
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RP2040 Datasheet • Motorola SPI • Texas Instruments SSI • National Semiconductor. The bit rate, derived from the external SSPCLK, requires the programming of the clock prescale register SSPCPSR. 4.5.3.3. Enable PrimeCell SSP operation You can either prime the transmit FIFO, by writing up to eight 16-bit values when the PrimeCell SSP is disabled, or permit the transmit FIFO service request to interrupt the CPU.
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RP2040 Datasheet • select the data word size, where applicable. The Serial Clock Rate (SCR) value, in conjunction with the SSPCPSR clock prescale divisor value, CPSDVSR, is used to derive the PrimeCell SSP transmit and receive bit rate from the external SSPCLK. The frame format is programmed through the FRF bits, and the data word size through the DSS bits. Bit phase and polarity, applicable to Motorola SPI format only, are programmed through the SPH and SPO bits. 4.5.3.6.
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RP2040 Datasheet Unlike the full-duplex transmission of the other two frame formats, the National Semiconductor Microwire format uses a special master-slave messaging technique that operates at half-duplex. In this mode, when a frame begins, an 8-bit control message is transmitted to the off-chip slave. During this transmit, the SSS receives no incoming data.
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RP2040 Datasheet 4.5.3.9.2. SPH, clock phase The SPH control bit selects the clock edge that captures data and enables it to change state. It has the most impact on the first bit transmitted by either permitting or not permitting a clock transition before the first data capture edge. When the SPH phase control bit is LOW, data is captured on the first clock edge transition. When the SPH clock phase control bit is HIGH, data is captured on the second clock edge transition. 4.5.3.10.
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RP2040 Datasheet SSPFSSOUT pin is returned to its idle state one SSPCLKOUT period after the last bit has been captured. 4.5.3.11. Motorola SPI Format with SPO=0, SPH=1 Figure 90 shows the transfer signal sequence for Motorola SPI format with SPO=0, SPH=1, and it covers both single and continuous transfers. Figure 90.
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RP2040 Datasheet  NOTE In Figure 91, Q is an undefined signal. Figure 92.
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RP2040 Datasheet  NOTE In Figure 93, Q is an undefined signal.
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RP2040 Datasheet • the nSSPOE pad enable signal is forced HIGH, making the transmit pad high impedance. A transmission is triggered by writing a control byte to the transmit FIFO. The falling edge of SSPFSSOUT causes the value contained in the bottom entry of the transmit FIFO to be transferred to the serial shift register of the transmit logic, and the MSB of the 8-bit control frame to be shifted out onto the SSPTXD pin. SSPFSSOUT remains LOW for the duration of the frame transmission.
PAGE 539
RP2040 Datasheet  NOTE The SSP (PL022) does not support dynamic switching between master and slave in a system. Each instance is configured and connected either as a master or slave. Figure 97 shows the PrimeCell SSP (PL022) instanced twice, as a single master and one slave. The master can broadcast to the slave through the master SSPTXD line. In response, the slave drives its nSSPOE signal HIGH, enabling its SSPTXD data onto the SSPRXD line of the master. Figure 97.
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RP2040 Datasheet Figure 99. SPI master coupled to a PrimeCell SSP slave SPI master PL022 configured as slave MOSI SSPRXD nSSPOE SSPTXD MISO SSPFSSIN OV SCK SSPFSSOUT SSPCLKIN Vdd SS nSSPCTLOE SSPCLKOUT 4.5.3.16. PrimeCell DMA interface The PrimeCell SSP provides an interface to connect to the DMA controller. The PrimeCell SSP DMA control register, SSPDMACR controls the DMA operation of the PrimeCell SSP.
PAGE 541
RP2040 Datasheet  NOTE For the remaining three characters, the PrimeCell SSP does not assert the burst request. Each request signal remains asserted until the relevant DMA clear signal is asserted. After the request clear signal is deasserted, a request signal can become active again, depending on the conditions that previous sections describe. All request signals are deasserted if the PrimeCell SSP is disabled, or the DMA enable signal is cleared.
PAGE 542
RP2040 Datasheet Description Control register 0, SSPCR0 on page 3-4 Table 525. SSPCR0 Register Bits Name Description Type Reset 31:16 Reserved. - - - 15:8 SCR Serial clock rate. The value SCR is used to generate the RW 0x00 RW 0x0 RW 0x0 RW 0x0 Data Size Select: 0000 Reserved, undefined operation. 0001 RW 0x0 transmit and receive bit rate of the PrimeCell SSP.
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RP2040 Datasheet SSPDR Register Description Data register, SSPDR on page 3-6 Table 527. SSPDR Register Bits Name Description Type Reset 31:16 Reserved. - - - 15:0 DATA Transmit/Receive FIFO: Read Receive FIFO. Write Transmit RWF - FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies.
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RP2040 Datasheet Bits Name Description Type Reset 3 TXIM Transmit FIFO interrupt mask: 0 Transmit FIFO half empty RW 0x0 Receive FIFO interrupt mask: 0 Receive FIFO half full or less RW 0x0 or less condition interrupt is masked. 1 Transmit FIFO half empty or less condition interrupt is not masked. 2 RXIM condition interrupt is masked. 1 Receive FIFO half full or less condition interrupt is not masked.
PAGE 545
RP2040 Datasheet Description Interrupt clear register, SSPICR on page 3-11 Table 533. SSPICR Register Bits Name Description Type Reset 31:2 Reserved. - - - 1 RTIC Clears the SSPRTINTR interrupt WC 0x0 0 RORIC Clears the SSPRORINTR interrupt WC 0x0 SSPDMACR Register Description DMA control register, SSPDMACR on page 3-12 Table 534. SSPDMACR Register Bits Name Description Type Reset 31:2 Reserved. - - - 1 TXDMAE Transmit DMA Enable.
PAGE 546
RP2040 Datasheet SSPPERIPHID3 Register Description Peripheral identification registers, SSPPeriphID0-3 on page 3-13 Table 538. SSPPERIPHID3 Register Bits Name Description Type Reset 31:8 Reserved. - - - 7:0 CONFIGURATION These bits read back as 0x00 RO 0x00 SSPPCELLID0 Register Description PrimeCell identification registers, SSPPCellID0-3 on page 3-16 Table 539. SSPPCELLID0 Register Bits Name Description Type Reset 31:8 Reserved.
PAGE 547
RP2040 Datasheet 4.6.1. Overview Pulse width modulation (PWM) is a scheme where a digital signal provides a smoothly varying average voltage. This is achieved with positive pulses of some controlled width, at regular intervals. The fraction of time spent high is known as the duty cycle. This may be used to approximate an analog output, or control switchmode power electronics. The RP2040 PWM block has 8 identical slices.
PAGE 548
RP2040 Datasheet • If a PWM B pin is used as an input, and is selected on multiple GPIO pins, then the PWM slice will see the logical OR of those two GPIO inputs 4.6.2.1. Pulse Width Modulation The PWM hardware functions by continuously comparing the input value to a free-running counter. This produces a toggling output where the amount of time spent at the high output level is proportional to the input value. The fraction of time spent at the high signal level is known as the duty cycle of the signal.
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RP2040 Datasheet Figure 103. The slice counts repeatedly Count from 0 to 3, which is 0 1 2 3 0 1 2 3 0 1 2 3 A configured as the TOP B value. The output waves therefore have a period of 4. Output A is high for 1 cycle in 4, The default behaviour of a PWM slice is to count upward until the value of the TOP register is reached, and then so the average output immediately wrap to 0.
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RP2040 Datasheet 4.6.2.3. Double Buffering Figure 106 shows how a change in input value will produce a change in output duty cycle. This can be used to approximate some analog waveform such as a sine wave. Figure 106. The input Input (Count) value varies with each counter period: first Count TOP Counter compare level TOP / 3, then 2 × TOP / 3, and finally TOP + 1 Counter 2×TOP/3 for 100% duty cycle.
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RP2040 Datasheet Figure 108. Each counter wrap causes the interrupt request Counter at top IRQ signal to assert. The processor enters its CC_A 0 interrupt handler, writes to its copy of CC_A latched 1 2 0 1 3 2 the CC register, and clears the interrupt. When the counter There is no limitation on what values can be written to CC or TOP, or when they are written.
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RP2040 Datasheet Figure 110. PWM slice Event select event selection. The Phase Advance Phase Retard counter advances when its enable input 1 is high, and this enable is generated in two sequential stages. Input (pin B) EN First, any one of four Fractional Clock Divider (8.4) Count enable Rising edge event types (always on, pin B high, pin B rise, pin B fall) can Falling edge generate enable pulses for the fractional clock divider.
PAGE 553
RP2040 Datasheet • The TOP register • Whether phase-correct mode is enabled (CSR_PH_CORRECT) • The DIV register The slice counts from 0 to TOP, and then either wraps, or begins counting backward, depending on the setting of CSR_PH_CORRECT. The rate of counting is slowed by the clock divider, with a maximum speed of one count per cycle, and a minimum speed of one count per cycles.
PAGE 554
RP2040 Datasheet Figure 111. The clock enable signal, output Clock by the clock divider, controls the rate of counting. Phase 2 DIV_INT advance forces the Clock enable clock enable high on Count cycles where it is low, 0 1 2 3 4 5 4 5 6 2 3 4 causing the counter to jump forward by one forces the clock 2 DIV_INT count. Phase retard CSR_PH_ADV enable low when it Clock enable would be high, holding the counter back by Count 0 1 2 3 one count.
PAGE 555
RP2040 Datasheet Offset Name Info 0x38 CH2_TOP Counter wrap value 0x3c CH3_CSR Control and status register 0x40 CH3_DIV INT and FRAC form a fixed-point fractional number. Counting rate is system clock frequency divided by this number. Fractional division uses simple 1st-order sigma-delta.
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RP2040 Datasheet Offset Name Info 0xa4 INTR Raw Interrupts 0xa8 INTE Interrupt Enable 0xac INTF Interrupt Force 0xb0 INTS Interrupt status after masking & forcing CH0_CSR, CH1_CSR, …, CH6_CSR, CH7_CSR Registers Description Control and status register Table 545. CH0_CSR, CH1_CSR, …, CH6_CSR, CH7_CSR Registers Bits Name Description Type Reset 31:8 Reserved. - - - 7 PH_ADV Advance the phase of the counter by 1 count, while it is SC 0x0 SC 0x0 RW 0x0 running. Self-clearing.
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RP2040 Datasheet Description Direct access to the PWM counter Table 547. CH0_CTR, CH1_CTR, …, CH6_CTR, CH7_CTR Registers Bits Name Description Type Reset 31:16 Reserved. - - - 15:0 NONAME RW 0x0000 Type Reset CH0_CC, CH1_CC, …, CH6_CC, CH7_CC Registers Description Counter compare values Table 548.
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RP2040 Datasheet Description Raw Interrupts Table 551. INTR Register Bits Name Description Type Reset 31:8 Reserved. - - - 7 CH7 WC 0x0 6 CH6 WC 0x0 5 CH5 WC 0x0 4 CH4 WC 0x0 3 CH3 WC 0x0 2 CH2 WC 0x0 1 CH1 WC 0x0 0 CH0 WC 0x0 INTE Register Description Interrupt Enable Table 552. INTE Register Bits Name Description Type Reset 31:8 Reserved.
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RP2040 Datasheet Bits Name 1 0 Description Type Reset CH1 RW 0x0 CH0 RW 0x0 INTS Register Description Interrupt status after masking & forcing Table 554. INTS Register Bits Name Description Type Reset 31:8 Reserved. - - - 7 CH7 RO 0x0 6 CH6 RO 0x0 5 CH5 RO 0x0 4 CH4 RO 0x0 3 CH3 RO 0x0 2 CH2 RO 0x0 1 CH1 RO 0x0 0 CH0 RO 0x0 4.7. Timer 4.7.1.
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RP2040 Datasheet can be used to read the raw time without any latching.  WARNING While it is technically possible to set the time by writing to the TIMEHW and TIMELW registers, programmers are discouraged from doing this. This is because the timer value is expected to be monotonically increasing (with a 64-bit wrap) by the Pico SDK which uses it for timeouts, elapsed time etc. 4.7.3. Alarms The timer has 4 alarms, and outputs a separate interrupt for each alarm.
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RP2040 Datasheet Pico Examples: https://github.com/raspberrypi/pico-examples/tree/pre_release/timer/timer_lowlevel/timer_lowlevel.c Lines 13 - 21 13 // Simplest form of getting 64 bit time from the timer.
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RP2040 Datasheet 40 41 static void alarm_in_us(uint32_t delay_us) { 42 // Enable the interrupt for our alarm (the timer outputs 4 alarm irqs) 43 hw_set_bits(&timer_hw->inte, 1u << ALARM_NUM); 44 // Set irq handler for alarm irq 45 irq_set_exclusive_handler(ALARM_IRQ, alarm_irq); 46 // Enable the alarm irq 47 irq_enable(ALARM_IRQ, true); 48 // Enable interrupt in block and at processor 49 50 // Alarm is only 32 bits so if trying to delay more 51 // than that need to be careful and keep trac
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RP2040 Datasheet 73 while (hi < hi_target) { 74 hi = timer_hw->timerawh; 75 tight_loop_contents(); 76 } 77 while (hi == hi_target && timer_hw->timerawl < (uint32_t) target) { 78 hi = timer_hw->timerawh; 79 tight_loop_contents(); 80 } 81 } 4.7.4.4. Complete example using Pico SDK Pico Examples: https://github.com/raspberrypi/pico-examples/tree/pre_release/timer/hello_timer/hello_timer.
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RP2040 Datasheet 55 printf("Done\n"); 56 return 0; 57 } 4.7.5. List of Registers Table 555. List of TIMER registers Offset Name Info 0x00 TIMEHW Write to bits 63:32 of time always write timelw before timehw 0x04 TIMELW Write to bits 31:0 of time writes do not get copied to time until timehw is written 0x08 TIMEHR Read from bits 63:32 of time always read timelr before timehr 0x0c TIMELR Read from bits 31:0 of time 0x10 ALARM0 Arm alarm 0, and configure the time it will fire.
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RP2040 Datasheet Description Write to bits 63:32 of time always write timelw before timehw Table 556. TIMEHW Register Bits Name 31:0 NONAME Description Type Reset WF 0x00000000 Type Reset WF 0x00000000 Type Reset RO 0x00000000 Type Reset RO 0x00000000 Type Reset RW 0x00000000 TIMELW Register Description Write to bits 31:0 of time writes do not get copied to time until timehw is written Table 557.
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RP2040 Datasheet Table 561. ALARM1 Register Bits Name 31:0 NONAME Description Type Reset RW 0x00000000 Type Reset RW 0x00000000 Type Reset RW 0x00000000 ALARM2 Register Description Arm alarm 2, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM2 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register. Table 562.
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RP2040 Datasheet Table 566. TIMERAWL Register Bits Name 31:0 NONAME Description Type Reset RO 0x00000000 DBGPAUSE Register Description Set bits high to enable pause when the corresponding debug ports are active Table 567. DBGPAUSE Register Bits Name Description Type Reset 31:3 Reserved. - - - 2 DBG1 Pause when processor 1 is in debug mode RW 0x1 1 DBG0 Pause when processor 0 is in debug mode RW 0x1 0 Reserved.
PAGE 568
RP2040 Datasheet INTF Register Description Interrupt Force Table 571. INTF Register Bits Name Description Type Reset 31:4 Reserved. - - - 3 ALARM_3 RW 0x0 2 ALARM_2 RW 0x0 1 ALARM_1 RW 0x0 0 ALARM_0 RW 0x0 INTS Register Description Interrupt status after masking & forcing Table 572. INTS Register Bits Name Description Type Reset 31:4 Reserved. - - - 3 ALARM_3 RO 0x0 2 ALARM_2 RO 0x0 1 ALARM_1 RO 0x0 0 ALARM_0 RO 0x0 4.8. Watchdog 4.8.1.
PAGE 569
RP2040 Datasheet  NOTE To avoid duplicating logic, this tick is also distributed to the timer (see Section 4.7) and used as the timer reference. The Pico SDK starts the watchdog tick at the start of day in clocks_init: Pico SDK: https://github.com/raspberrypi/pico-sdk/tree/pre_release/src/rp2_common/hardware_watchdog/watchdog.
PAGE 570
RP2040 Datasheet 48 hw_set_bits(&watchdog_hw->ctrl, dbg_bits); 49 } else { 50 hw_clear_bits(&watchdog_hw->ctrl, dbg_bits); 51 } 52 53 if (!delay_ms) delay_ms = 50; 54 55 if (delay_ms > 0x7fffff) 56 delay_ms = 0x7fffff; 57 58 // Note, we have x2 here as the watchdog HW currently decrements twice per tick 59 load_value = delay_ms * 1000 * 2; 60 61 watchdog_update(); 62 63 hw_set_bits(&watchdog_hw->ctrl, WATCHDOG_CTRL_ENABLE_BITS); 64 } 4.8.5.2.
PAGE 571
RP2040 Datasheet 32 while(1); 33 } 4.8.6. List of registers Table 573. List of WATCHDOG registers Offset Name Info 0x00 CTRL Watchdog control The rst_wdsel register determines which subsystems are reset when the watchdog is triggered. The watchdog can be triggered in software. 0x04 LOAD Load the watchdog timer. The maximum setting is 0xffffff which corresponds to 0xffffff / 2 ticks before triggering a watchdog reset (see errata RP2040-E1). 0x08 REASON Logs the reason for the last reset.
PAGE 572
RP2040 Datasheet Bits Name Description Type Reset 26 PAUSE_DBG1 Pause the watchdog timer when processor 1 is in debug RW 0x1 RW 0x1 Pause the watchdog timer when JTAG is accessing the bus RW 0x1 mode 25 PAUSE_DBG0 Pause the watchdog timer when processor 0 is in debug mode 24 PAUSE_JTAG fabric 23:0 TIME Indicates the number of ticks / 2 (see errata RP2040-E1) RO 0x000000 before a watchdog reset will be triggered LOAD Register Description Load the watchdog timer.
PAGE 573
RP2040 Datasheet Bits Name Description Type Reset 8:0 CYCLES Total number of clk_tick cycles before the next tick. RW 0x000 4.9. RTC The Real-time Clock (RTC) provides time in human-readable format and can be set to generate events at specific times. Time is stored in binary, separated in seven fields: Table 579. RTC storage format Date/Time Field Size Legal values Year 12 bits 0..4095 Month 4 bits 1..12 Day 5 bits 1..[28,29,30,31], depending on the month Day of Week 3 bits 0..6.
PAGE 574
RP2040 Datasheet 4.9.2. Leap year If the current value of YEAR in SETUP_0 is evenly divisible by 4, a leapyear is detected, and Feb 28th is followed by Feb 29th, not March 1st. Since this is not always true (century years for example), the leapyear checking can be forced off by setting the CTRL.FORCE_NOTLEAPYEAR. The next occurrence when this should happen is in year 2100.  NOTE The leap year check is done only when needed (the second following Feb 28, 23:59:59).
PAGE 575
RP2040 Datasheet  NOTE While it is possible to change the CLKDIV_M1 on the fly, it is not recommended. 4.9.4.2. Setting up the clock Write a near-future time to RTC setup registers. Write a 1 to the LOAD bit in the CTRL register, (this bit is self-clearing). Then, at the appropriate time, enable the RTC using the ENABLE bit in the CTRL register. The RTC_ACTIVE bit in CTRL can be read to confirm the RTC is running. 4.9.4.2.1.
PAGE 576
RP2040 Datasheet IRQ_SETUP_0.MATCH_ACTIVE = 1  NOTE The enable matching step can be done during the write to IRQ_SETUP_0, as long as it happens after the write to IRQ_SETUP_1 4.9.4.5. Recurring alarm TO DO: LIAM/ANDRAS: sample code? The interrupt setup registers are used to set a specific date and time for an interrupt to happen. To set up a recurring alarm for every Monday at 11:00am: Turn off global matching. IRQ_SETUP_0 Disable matching with an atomic write: IRQ_SETUP_0.
PAGE 577
RP2040 Datasheet 4.9.5.1. Initialise the RTC Pico SDK: https://github.com/raspberrypi/pico-sdk/tree/pre_release/src/rp2_common/hardware_rtc/rtc.
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RP2040 Datasheet 85 86 tight_loop_contents(); } 87 88 return 0; 89 } 4.9.5.3. Get the time Pico SDK: https://github.com/raspberrypi/pico-sdk/tree/pre_release/src/rp2_common/hardware_rtc/rtc.
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RP2040 Datasheet 140 141 // Enable the IRQ at the proc 142 irq_enable(RTC_IRQ, true); 143 144 // Set matching and wait for it to be enabled 145 hw_set_bits(&rtc_hw->irq_setup_0, RTC_IRQ_SETUP_0_MATCH_ENA_BITS); 146 while(!(rtc_hw->irq_setup_0 & RTC_IRQ_SETUP_0_MATCH_ACTIVE_BITS)); 147 } 4.9.5.5. Complete Pico SDK example Pico Examples: https://github.com/raspberrypi/pico-examples/tree/pre_release/rtc/hello_rtc/hello_rtc.
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RP2040 Datasheet Offset Name Info 0x0c CTRL RTC Control and status 0x10 IRQ_SETUP_0 Interrupt setup register 0 0x14 IRQ_SETUP_1 Interrupt setup register 1 0x18 RTC_1 RTC register 1. 0x1c RTC_0 RTC register 0 Read this before RTC 1! 0x20 INTR Raw Interrupts 0x24 INTE Interrupt Enable 0x28 INTF Interrupt Force 0x2c INTS Interrupt status after masking & forcing CLKDIV_M1 Register Description Divider minus 1 for the 1 second counter.
PAGE 581
RP2040 Datasheet Bits Name Description Type Reset 13:8 MIN Minutes RW 0x00 7:6 Reserved. - - - 5:0 SEC Seconds RW 0x00 CTRL Register Description RTC Control and status Table 584. CTRL Register Bits Name Description Type Reset 31:9 Reserved. - - - 8 FORCE_NOTLEAP If set, leapyear is forced off. RW 0x0 YEAR Useful for years divisible by 100 but not by 400 7:5 Reserved. - - - 4 LOAD Load RTC SC 0x0 3:2 Reserved.
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RP2040 Datasheet Table 586. IRQ_SETUP_1 Register Bits Name Description Type Reset 31 DOTW_ENA Enable day of the week matching RW 0x0 30 HOUR_ENA Enable hour matching RW 0x0 29 MIN_ENA Enable minute matching RW 0x0 28 SEC_ENA Enable second matching RW 0x0 27 Reserved. - - - 26:24 DOTW Day of the week RW 0x0 23:21 Reserved. - - - 20:16 HOUR Hours RW 0x00 15:14 Reserved. - - - 13:8 MIN Minutes RW 0x00 7:6 Reserved.
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RP2040 Datasheet Description Raw Interrupts Table 589. INTR Register Bits Name Description Type Reset 31:1 Reserved. - - - 0 RTC RO 0x0 INTE Register Description Interrupt Enable Table 590. INTE Register Bits Name Description Type Reset 31:1 Reserved. - - - 0 RTC RW 0x0 INTF Register Description Interrupt Force Table 591. INTF Register Bits Name Description Type Reset 31:1 Reserved.
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RP2040 Datasheet • Four element receive sample FIFO • Interrupt generation • DMA interface  NOTE When using an ADC input shared with a GPIO pin, the pin’s digital functions must be disabled by setting IE low and OD high in the pin’s pad control register. See Section 2.18.6.3, “Pad Control - User Bank” for details. The maximum ADC input voltage is determined by the digital IO supply voltage (IOVDD), not the ADC supply voltage (ADC_IOVDD). For example, if IOVDD is powered at 1.
PAGE 585
RP2040 Datasheet 4.10.3. SAR ADC The SAR ADC (Successive Approximation Register Analogue to Digital Converter) is a combination of digital controller, and analogue circuit as show in Figure 113. Figure 113. SAR ADC Block diagram The ADC requires a 48MHz clock ( clk_adc ), which could come from the USB PLL. Capturing a sample takes 96 clock cycles (96 x 1 / 48MHz) = 2 μs per sample (500kS/s). The clock must be set up correctly before enabling the ADC.
PAGE 586
RP2040 Datasheet 4.10.3.3. Sampling Multiple Inputs CS.RROBIN allows the ADC to sample multiple inputs, in an interleaved fashion, while performing free-running sampling. Each bit in RROBIN corresponds to one of the five possible values of CS.AINSEL. When the ADC completes a conversion, >.AINSEL will automatically cycle to the next input whose corresponding bit is set in RROBIN. The round-robin sampling feature is disabled by writing all-zeroes to CS.RROBIN.
PAGE 587
RP2040 Datasheet 4.10.3.6. Interrupts An interrupt can be generated when the FIFO level reaches a configurable threshold FCS.THRESH. The interrupt output must be enabled via INTE. Status can be read from INTS. The interrupt is cleared by draining the FIFO to a level lower than FCS.THRESH. 4.10.3.7. Supply The ADC supply is separated out on its own pin to allow noise filtering. 4.10.4.
PAGE 588
RP2040 Datasheet Bits Name Description Type Reset 20:16 RROBIN Round-robin sampling. 1 bit per channel. Set all bits to 0 to RW 0x00 disable. Otherwise, the ADC will cycle through each enabled channel in a round-robin fashion. The first channel to be sampled will be the one currently indicated by AINSEL. AINSEL will be updated after each conversion with the newly-selected channel. 15 Reserved. - - - 14:12 AINSEL Select analog mux input. Updated automatically in round- RW 0x0 robin mode.
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RP2040 Datasheet Bits Name Description Type Reset 23:20 Reserved. - - - 19:16 LEVEL The number of conversion results currently waiting in the RO 0x0 FIFO 15:12 Reserved. - - - 11 OVER 1 if the FIFO has been overflowed. Write 1 to clear. WC 0x0 10 UNDER 1 if the FIFO has been underflowed. Write 1 to clear. WC 0x0 9 FULL RO 0x0 8 EMPTY RO 0x0 7:4 Reserved.
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RP2040 Datasheet Description Raw Interrupts Table 599. INTR Register Bits Name Description Type Reset 31:1 Reserved. - - - 0 FIFO Triggered when the sample FIFO reaches a certain level. RO 0x0 This level can be programmed via the FCS_THRESH field. INTE Register Description Interrupt Enable Table 600. INTE Register Bits Name Description Type Reset 31:1 Reserved. - - - 0 FIFO Triggered when the sample FIFO reaches a certain level.
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RP2040 Datasheet 4.11.1. Overview In order for the DW_apb_ssi to connect to a serial-master or serial-slave peripheral device, the peripheral must have a least one of the following interfaces: Motorola Serial Peripheral Interface (SPI) A four-wire, full-duplex serial protocol from Motorola. There are four possible combinations for the serial clock phase and polarity.
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RP2040 Datasheet • Motorola Serial Peripheral Interface (SPI) • Texas Instruments Serial Protocol (SSP) • National Semiconductor Microwire On RP2040, the DW_apb_ssi is a component of the flash execute-in-place subsystem (see Execute-In-Place), and provides communication with an external SPI, dual-SPI or quad-SPI flash device. 4.11.2.1.
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RP2040 Datasheet 4.11.3.1. Example of Target Slave Selection Using Software The following example is pseudo code that illustrates how to use software to select the target slave.
PAGE 594
RP2040 Datasheet Figure 115. Maximum capture sclk_out/ssi_clk Ratio. drive1 capture1 drive2 capture2 drive3 capture3 ssi_clk sclk_out txd/rxd MSB The sclk_out line toggles only when an active transfer is in progress. At all other times it is held in an inactive state, as defined by the serial protocol under which it operates.
PAGE 595
RP2040 Datasheet Table 603 provides description for different Transmit FIFO Threshold values. Table 603.
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RP2040 Datasheet Transmit FIFO Overflow Interrupt (ssi_txo_intr) Set when an APB access attempts to write into the transmit FIFO after it has been completely filled. When set, data written from the APB is discarded. This interrupt remains set until you read the transmit FIFO overflow interrupt clear register (TXOICR). Receive FIFO Full Interrupt (ssi_rxf_intr) Set when the receive FIFO is equal to or above its threshold value plus 1 and requires service to prevent an overflow.
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RP2040 Datasheet 4.11.8.3. Receive Only When TMOD = 10b, the transmit data are invalid. When configured as a slave, the transmit FIFO is never popped in Receive Only mode. The txd output remains at a constant logic level during the transmission. The data transfer occurs as normal according to the selected frame format (serial protocol). The receive data from the target device is moved from the receive shift register into the receive FIFO at the end of each data frame.
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RP2040 Datasheet Figure 116. DW_apb_ssi DW_apb_ssi Master 1 Configured as Master Device Slave Peripheral 1 DI txd DO ssi_oe_n SCLK rxd SS sclk_out ss_n[0] Slave Peripheral n ss_n[1] ss_in_n DI DO Glue Logic SCLK SS Should be driven to inactive level (protocol-dependent) in single master systems; may not need glue logic The serial bit-rate clock, generated and controlled by the DW_apb_ssi, is driven out on the sclk_out line.
PAGE 599
RP2040 Datasheet the setup times on the rxd signal are within range; this results in reducing the frequency of the serial interface. When the RXD Sample Delay logic is included, the user can dynamically program a delay value in order to move the sampling time of the rxd signal equal to a number of ssi_clk cycles from the default. The sample delay logic has a resolution of one ssi_clk cycle.
PAGE 600
RP2040 Datasheet  NOTE EEPROM read mode is not supported when the DW_apb_ssi is configured to be in the SSP mode. The receive FIFO threshold level (RXFTLR) can be used to give early indication that the receive FIFO is nearly full. When a DMA is used for APB accesses, the receive data level (DMARDLR) can be used to early request (dma_rx_req) the DMA Controller, indicating that the receive FIFO is nearly full.
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RP2040 Datasheet Figure 118. Software Flow DW_apb_ssi Master SPI/SSP Transfer Flow IDLE Disable DW_apb_ssi DW_apb_ssi IDLE Configure Master by writing CTRLR0. CTRLR1, BAUDR, TXFTLR, RXFTLR, IMR, SER, SPI_CTRLR0 (if Dual /Quad SPI) Pop data from Tx FIFO into shifter Enable DW_apb_ssi Transfer Bit You may fill FIFO here: Transfer begins when first data word is present in the transmit FIFO and slave is enabled.
PAGE 602
RP2040 Datasheet You can write the SER register to enable the target slave for selection. If a slave is enabled here, the transfer begins as soon as one valid data entry is present in the transmit FIFO. If no slaves are enabled prior to writing to the DR register, the transfer does not begin until a slave is enabled. 3. Enable the DW_apb_ssi by writing 1 to the SSIENR register. 4. If the DW_apb_ssi master transmits data, write the control and data words into the transmit FIFO (write DR).
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RP2040 Datasheet is high or low. To transmit data, both SPI peripherals must have identical serial clock phase (SCPH) and clock polarity (SCPOL) values. The data frame can be 4 to 16/32 bits (depending upon SSI_MAX_XFER_SIZE) in length. When the configuration parameter SCPH = 0, data transmission begins on the falling edge of the slave select signal.
PAGE 604
RP2040 Datasheet Figure 122 shows the timing diagram for the SPI format when the configuration parameter SCPH = 1. Figure 122. SPI Serial Format (SCPH = 1) sclk_out/in 0 sclk_out/in 1 txd MSB rxd MSB LSB 4 -32 bits LSB ss_0_n/ss_in_n ssi_oe_n Continuous data frames are transferred in the same way as single frames, with the MSB of the next frame following directly after the LSB of the current frame. The slave select signal is held active for the duration of the transfer.
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RP2040 Datasheet Figure 125.
PAGE 606
RP2040 Datasheet Figure 127. FIFO rxd Status for EEPROM Read Transfer Mode Write DR Tx FIFO Empty Tx FIFO Buffer Location n NULL Location 3 NULL Location n NULL SHIFT LOGIC Location 2 Address[7:0] Location 7 Rx_Data(7) Location 1 Address[15:8] Location 6 Rx_Data(6) Location 0 Opcode Location 1 Rx_Data(1) Location 0 Rx_Data(0) Rx FIFO Empty FIFO Status Prior to Transfer Rx FIFO Buffer txd Read DR FIFO Status on Completion of Transfer 4.11.10.2.
PAGE 607
RP2040 Datasheet The direction of the data word is controlled by the MDD bit field (bit 1) in the Microwire Control Register (MWCR). When MDD=0, this indicates that the DW_apb_ssi serial master receives data from the external serial slave. One clock cycle after the LSB of the control word is transmitted, the slave peripheral responds with a dummy 0 bit, followed by the data frame, which can be four to 32 bits in length.
PAGE 608
RP2040 Datasheet Figure 133.
PAGE 609
RP2040 Datasheet Figure 136. Single Microwire Transfer sclk_out (transmitting data Control word frame) MSB txd Data word 0 LSB LSB MSB rxd ss_0_n ssi_oe_n  NOTE The DW_apb_ssi does not support continuous sequential Microwire writes, where MDD = 1 and MWMOD = 1. Figure 137 shows how the data and control frames are structured in the transmit FIFO prior to the transfer, also shown is the value programmed into the MWCR register. Figure 137.
PAGE 610
RP2040 Datasheet Figure 139.
PAGE 611
RP2040 Datasheet Figure 142. Microwire Control Word sclk_out Control Word 0 txd MSB LSB rxd Start Bit Busy Ready ss_0_n ssi_oe_n 4.11.10.4. Enhanced SPI Modes DW_apb_ssi supports the dual and quad modes of SPI in RP2040; octal mode is not supported. txd, rxd and ssi_oe_n signals are four bits wide. Data is shifted out/in on more than one line, increasing the overall throughput.
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RP2040 Datasheet Figure 143. Typical Write Operation Dual/Quad SPI Mode sclk_out txd[N:0] INSTRUCTION ADDRESS DATA ssi_oe_n[N:0] ss_oe_n To initiate a Dual/Quad write operation, CTRLR0.SPI_FRF must be set to 01/10/11, respectively. This will set the transfer type, and for each write command, data will be transferred in the format specified in CTLR0.SPI_FRF field. Case A: Instruction and address both transmitted in standard SPI format For this, SPI_CTRLR0.TRANS_TYPE field must be set to 00b.
PAGE 613
RP2040 Datasheet 4.11.10.4.2. Read Operation in Enhanced SPI Modes A Dual, or Quad, SPI read operation can be divided into four phases: • Instruction phase • Address phase • Wait cycles • Data phase Wait Cycles can be programmed using SPI_CTRLR0.WAIT_CYCLES field. The value programmed into SPI_CTRLR0.WAIT_CYCLES is mapped directly to sclk_out times. For example, WAIT_CYCLES=0 indicates no Wait, WAIT_CYCLES=1, indicates one wait cycle and so on.
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RP2040 Datasheet Case C: Instruction and Address both transmitted in Dual SPI format For this, SPI_CTRLR0.TRANS_TYPE field must be set to 10b. Figure 151 shows the timing diagram in which both instruction and address are transmitted in dual SPI format. The value of N will be: 7 if CTRLR0.SPI_FRF is set to 11b, 3 if CTRLR0.SPI_FRF is set to 10b, and 1 if CTRLR0.SPI_FRF is set to 01b. Figure 151.
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RP2040 Datasheet 4.11.10.4.3. Advanced I/O Mapping for Enhanced SPI Modes The Input/Output mapping for enhanced SPI modes (dual, and quad) is hardcoded inside the DW_apb_ssi. The rxd[1] signal will be used to sample incoming data in standard SPI mode of operation. For other protocols (such as SSP and Microwire), the I/O mapping remains the same.
PAGE 616
RP2040 Datasheet Figure 154. DDR Transfer with SCPH=0 sclk_out and SCPOL=0 ss_oe_n A3 INST txd[N:0] A2 A1 A0 D3 D2 D1 D0 rxd[N:0] ss_oe_n[N:0] INST = Instruction Phase A3, A2, A1, A0 = Address Bytes D3, D2, D1, D0 = Data Bytes Figure 155 describes a DDR write transfer where instruction, address and data all are transferred in DDR format. Figure 155.
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RP2040 Datasheet Figure 157. Transmit Data With DDR_DRIVE_EDGE = 1 ssi_clk sclk_out ss_0_n txd[N:0] INST A3 A2 A1 A0 D3 D2 D1 D0 rxd[N:0] ssi_oe_n[N:0] INST = Instruction Phase A3, A2, A1, A0 = Address Bytes D3, D2, D1, D0 = Data Bytes Figure 158. Transmit Data With DDR_DRIVE_EDGE = 2 ssi_clk sclk_out ss_0_n txd[N:0] INST A3 A2 A1 A0 D3 D2 D1 D0 rxd[N:0] ssi_oe_n[N:0] INST = Instruction Phase A3, A2, A1, A0 = Address Bytes D3, D2, D1, D0 = Data Bytes 4.11.10.6.
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RP2040 Datasheet Figure 159. Typical pclk Read Operation in XIP Mode xip_en psel penable 0×00 paddr pready D1 prdata[31:0] ss_x_n sclk_out 0×00 txd[7:0] D1 rxd[7:0] 4.11.11. DMA Controller Interface The DW_apb_ssi has built-in DMA capability; it has a handshaking interface to a DMA Controller to request and control transfers. The APB bus is used to perform the data transfer to or from the DMA.
PAGE 619
RP2040 Datasheet 0000_0010 dma_tx_req is asserted when two or less data entries are present in the transmit FIFO … … 0000_1101 dma_tx_req is asserted when 13 or less data entries are present in the transmit FIFO 0000_1110 dma_tx_req is asserted when 14 or less data entries are present in the transmit FIFO 0000_1111 dma_tx_req is asserted when 15 or less data entries are present in the transmit FIFO Table 607 provides description for different DMA Receive Data Level values. Table 607.
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RP2040 Datasheet If the DW_apb_ssi makes a transmit request to this channel, four data items are written to the DW_apb_ssi transmit FIFO. Similarly, if the DW_apb_ssi makes a receive request to this channel, four data items are read from the DW_apb_ssi receive FIFO. Three separate requests must be made to this DMA channel before all 12 data items are written or read.
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RP2040 Datasheet TO DO: I’m not sure the above section is useful to me a user of the rp2040, if it is what do I do with it 4.11.13. List of Registers Table 608.
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RP2040 Datasheet Table 609. CTRLR0 Register Bits Name Description Type Reset 31:25 Reserved. - - - 24 SSTE Slave select toggle enable RW 0x0 23 Reserved.
PAGE 623
RP2040 Datasheet Table 611. SSIENR Register Bits Name Description Type Reset 31:1 Reserved. - - - 0 SSI_EN SSI enable RW 0x0 MWCR Register Description Microwire Control Table 612. MWCR Register Bits Name Description Type Reset 31:3 Reserved. - - - 2 MHS Microwire handshaking RW 0x0 1 MDD Microwire control RW 0x0 0 MWMOD Microwire transfer mode RW 0x0 SER Register Description Slave enable Table 613. SER Register Bits Name Description Type Reset 31:1 Reserved.
PAGE 624
RP2040 Datasheet Table 616. RXFTLR Register Bits Name Description Type Reset 31:8 Reserved. - - - 7:0 RFT Receive FIFO threshold RW 0x00 TXFLR Register Description TX FIFO level Table 617. TXFLR Register Bits Name Description Type Reset 31:8 Reserved. - - - 7:0 TFTFL Transmit FIFO level RO 0x00 RXFLR Register Description RX FIFO level Table 618. RXFLR Register Bits Name Description Type Reset 31:8 Reserved.
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RP2040 Datasheet Bits Name Description Type Reset 2 RXUIM Receive FIFO underflow interrupt mask RW 0x0 1 TXOIM Transmit FIFO overflow interrupt mask RW 0x0 0 TXEIM Transmit FIFO empty interrupt mask RW 0x0 ISR Register Description Interrupt status Table 621. ISR Register Bits Name Description Type Reset 31:6 Reserved.
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RP2040 Datasheet Description RX FIFO overflow interrupt clear Table 624. RXOICR Register Bits Name Description Type Reset 31:1 Reserved. - - - 0 NONAME Clear-on-read receive FIFO overflow interrupt RO 0x0 RXUICR Register Description RX FIFO underflow interrupt clear Table 625. RXUICR Register Bits Name Description Type Reset 31:1 Reserved. - - - 0 NONAME Clear-on-read receive FIFO underflow interrupt RO 0x0 MSTICR Register Description Multi-master interrupt clear Table 626.
PAGE 627
RP2040 Datasheet Table 629. DMATDLR Register Bits Name Description Type Reset 31:8 Reserved. - - - 7:0 DMATDL Transmit data watermark level RW 0x00 DMARDLR Register Description DMA RX data level Table 630. DMARDLR Register Bits Name Description Type Reset 31:8 Reserved. - - - 7:0 DMARDL Receive data watermark level (DMARDLR+1) RW 0x00 IDR Register Description Identification register Table 631.
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RP2040 Datasheet Description SPI control Table 635. SPI_CTRLR0 Register Bits Name Description Type Reset 31:24 XIP_CMD SPI Command to send in XIP mode (INST_L = 8-bit) or to RW 0x03 append to Address (INST_L = 0-bit) 23:19 Reserved.
PAGE 629
RP2040 Datasheet Chapter 5. Electrical and Mechanical Physical and electrical details of the RP2040 chip. 5.1. Package Figure 162. Top down view (left, top) and side view (right, top), along with bottom view (left, bottom) of the RP2040 QFN-56 package PIN 1  NOTE There is no standard size for the central GND pad (or ePad) with QFNs. However, the one on RP2040 is smaller than most. This means that standard 0.4mm QFN-56 footprints provided with CAD tools may need adjusting.
PAGE 630
RP2040 Datasheet Figure 163. Recommended PCB 7.75 Footprint for the 6.00 RP2040 QFN-56 3.20 package 0.20 7.75 6.00 3.20 5.40 0.20 1.175 0.875 0.40 5.40 Dimensions in mm 5.2. Pinout 5.2.1. Pin Locations Figure 164.
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RP2040 Datasheet 5.2.2. Pin Definitions 5.2.2.1. Pin Types In the following GPIO Pin table, the pin types are defined as shown below. Table 637. Pin Types Pin Type Direction Description Digital In Input only Standard Digital. Programmable Pull-Up, Pull-Down, Slew Rate, Schmitt Digital IO Bi-directional Digital In (FT) Input only Trigger and Drive Strength. Default Drive Strength is 4mA. Fault Tolerant Digital.
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RP2040 Datasheet Name Number Type Power Domain Reset State Description GPIO16 27 Digital IO (FT) IOVDD Pull-Down User IO GPIO17 28 Digital IO (FT) IOVDD Pull-Down User IO GPIO18 29 Digital IO (FT) IOVDD Pull-Down User IO GPIO19 30 Digital IO (FT) IOVDD Pull-Down User IO GPIO20 31 Digital IO (FT) IOVDD Pull-Down User IO GPIO21 32 Digital IO (FT) IOVDD Pull-Down User IO GPIO22 34 Digital IO (FT) IOVDD Pull-Down User IO GPIO23 35 Digital IO (FT) IOVDD Pull-D
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RP2040 Datasheet Table 641. Serial wire debug pins Table 642. Miscellaneous pins Name Number Type Power Domain Reset State Description SWCLK 24 Digital In (FT) IOVDD Pull-Up Debug clock SWD 25 Digital IO (FT) IOVDD Pull-Up Debug data Name Number Type Power Domain Reset State Description RUN 26 Digital In (FT) IOVDD Pull-Up Chip enable / reset TESTEN 19 Digital In IOVDD Pull-Down Test enable (connect to Gnd) Table 643.
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RP2040 Datasheet 5.2.3.2. ESD Performance Table 646. ESD performance for all pins, unless otherwise stated Parameter Symbol Maximum Units Comment HBM 2 kV Compliant with JEDEC Human Body Model specification JS-0012012 (April 2012) Human Body Model HBM 4 kV Compliant with JEDEC Digital (FT) pins only specification JS-0012012 (April 2012) Charged Device Model CDM 500 V Compliant with JESD22-C101E (December 2009) 5.2.3.3. Thermal Performance Table 647.
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RP2040 Datasheet Parameter Output Voltage Symbol Minimum Maximum Units VOH 1.24 IOVDD V High @ on setting VOH 1.78 IOVDD V High @ on setting VOH 2.62 IOVDD V High @ on setting VOL 0 0.3 V Low @ on setting VOL 0 0.4 V Low @ IOL = 2, 4, 8 or 12mA depending IOVDD=2.5V Output Voltage IOL = 2, 4, 8 or 12mA depending IOVDD=1.8V Output Voltage IOH = 2, 4, 8 or 12mA depending IOVDD=3.3V Output Voltage IOH = 2, 4, 8 or 12mA depending IOVDD=2.
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RP2040 Datasheet Table 650. ADC characteristics Parameter Symbol Minimum Maximum Units ADC Input Voltage VPIN_ADC 0 ADC_IOVDD V ENOB 9 Comment Range Effective Number bits Simulated of Bits Resolved Bits Table 651. Oscillator pin characteristics when using a Square Wave input Parameter Input Voltage High 12 bits Symbol Minimum Maximum Units Comment VIH 0.65*IOVDD IOVDD + 0.3 V XIN only. XOUT floating Input Voltage Low VIL 0 0.35*IOVDD V XIN only.
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RP2040 Datasheet Figure 165. Typical Current vs Voltage curves of a GPIO output. Figure 165 shows the effect on the output voltage as the current load on the pin increases. You can clearly see the effect of the different drive strengths; the higher the drive strength, the closer the output voltage is to IOVDD (or 0V) for a given current. The minimum VOH and maximum VOL limits are shown in red.
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RP2040 Datasheet 5.4. Power Consumption The following data shows the current consumption of various power supplies on 3 each of typical (tt), fast (ff) and slow (ss) corner RP2040 devices, with four different software use-cases.  NOTE For power consumption of the Raspberry Pi Pico, please see the Raspberry Pi Pico Datasheet. Firstly, 'Popcorn' (Media player demo) using the VGA, SD Card, and Audio board. This demo uses VGA video, I2S aduio and 4-bit SD Card access, with a system clock frequency of 48MHz.
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RP2040 Datasheet Figure 166. DVDD Current vs Core Frequency of a typical RP2040 device, whilst running FFT calculations 5.4.
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RP2040 Datasheet Appendix A: Register Field Types Standard types RW The processor can write to this field and read the value back. RO The processor can only read this field. WO The processor can only write to this field. Clear types SC This is a single bit that is written to by the processor and then cleared on the next clock cycle. An example use of this would be a start bit that triggers an event, and then clears again so the event doesn’t keep triggering.
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RP2040 Datasheet WF Implementation defined write to the hardware. RWF Implementation defined read to, and write from the hardware.
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RP2040 Datasheet Appendix B: Errata Watchdog RP2040-E1 Reference RP2040-E1 Summary Watchdog count is decremented twice per tick. Description The watchdog (Section 4.8) has a 24 bit counter, that decrements every tick, starting from a user defined value set in LOAD register. There is a logic error which means the counter is decremented twice per tick, instead of once per tick.
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RP2040 Datasheet Description The USB host has two types of transactions: normal software initiated transfer, and interrupt transfers, where the host polls an interrupt endpoint after a specific amount of time. For example, polling a mouse every 1ms to check for movement. Interrupt transfer are single buffered, but the controller doesn’t reset the buffer selector to zero.
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RP2040 Datasheet Description The USB bus RESET state is triggered by the host sending SE0 for 10ms to the device. The USB device controller requires 800μs of idle (J-state) after a bus reset before moving to the CONNECTED state. Without this idle time, the USB device does not connect and will not receive any packets from the host, and so does not enumerate. A device reset happens just after the device is plugged in.
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RP2040 Datasheet GPIO / ADC Affects RP2040B0, RP2040B1 Fixed by Software. Fixed in Pico SDK, custom user code will need to take note.
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