Datasheet

9
The sub-sections that will follow describe the functions of the various blocks depicted in Figure 1 that are present on the
ARTIK 530 Module.
The ARTIK 530 Module provides a GPIO system with up to 107 GPIOs (76 multiplexed, 31 dedicated) to allow for a wide variety
of use cases to be supported. The key features of the GPIO system are:
 Programmable pull-up control
 Both edge detect and level detect functionality
 Support for programmable pull-up resistors
 Support for fast or normal slew operation
 Support for default Drive Strength or High Drive Strength
 Support for interrupt generation that can be triggered on:
 Rising edge
 Falling edge
 High level detection
 Low level detection
 The I/O data is clocked up to 50MHz
The ARTIK 530 Module provides two 5-line Inter-IC Sound (I
2
S) channel. I
2
S is one of the most popular digital audio interfaces.
The I
2
S bus handles audio data and other signals, such as sub-coding and control. It is possible to transmit data between two
I
2
S buses. The key features of the I
2
S sub-system are:
 Supports 1-port stereo (1 channel) I
2
S-bus for audio with DMA based operation
 Supports serial data transfer of 16/24-bit per channel in Master and Slave mode
 Supports a variety of interface modes:
 I
2
S, Left justified, Right justified, DSP mode
The ARTIK 530 Module provides two pulse width modulation (PWM) modules. The key features of the PWM modules are:
 Two individual PWM channels with independent duty control and polarity
 Two 32-bit PWM timers, one per channel
 Support for static as well as dynamic setup
 Support for auto-reload and one shot pulse mode
 Dead zone generator
 Level interrupt generation
The ARTIK 530 Module provides two, Serial Peripheral Interfaces (SPI) that transfers serial data. SPI support includes
8-bit/16-bit shift registers to transmit and receive data. During an SPI transfer, data is simultaneously transmitted (shifted out
serially) and received (shifted in serially). The SPI implementation adheres to the protocols described by Texas Instruments
Synchronous Serial, National Semiconductor’s Microwire and Motorola’s Serial Peripheral Interface. The key features of the
SPI sub-system are:
 Support for full-duplex
 8-bit/16-bit shift register for Tx and Rx
 Complies with the SPI protocol described by Texas Instruments, National Semiconductor and Motorola
 Support for independent 16-bit wide transmit and receive FIFOs 8 locations deep
 Supports for master mode and slave mode
 Supports for receive-without-transmit operation
 Max operating frequency :
 Master Mode : Support Tx up to 50MHz, Rx up to 20MHz