Datasheet

51
I
2
C BUS Controller Module Signal Timing
(VDDINT, VDDarm = 1.1 V ± 5 %, T
J
= -25 to 85°C, VDDext = 3.3 V ± 10 %)
Parameter
Symbol
Min.
Typ.
Max.
Unit
SCL clock frequency
F
SCL
–
–
std. 100
fast 400
kHz
SCL high level pulse width
T
SCLHIGH
std. 4.0
fast 0.6
–
–
s
SCL low level pulse width
T
SCLLOW
std. 4.7
fast 1.3
–
–
Bus free time between STOP and START
T
BUF
std 4.7
fast 1.3
–
–
START hold time
T
STARTS
std. 4.0
fast 0.6
–
–
SDA hold time
T
SDAH
std. 0
fast 0
–
std.
fast 0.9
SDA setup time
T
SDAS
std. 250
fast 100
–
–
ns
STOP setup time
T
STOPH
std. 4.0
fast 0.6
–
–
s
Note: std. refers to Standard Mode and fast refers to Fast Mode.
1. The I
2
C data hold time (t
SDAH
) is minimum 0ns.
(I
2
C data hold time is minimum 0ns for standard/fast bus mode I
2
C specification v2.1)
Check whether the data hold time of your I
2
C device is 0 ns or not.
2. The I
2
C controller supports I
2
C bus device only (standard/fast bus mode), and does not support C bus device.
IICSCL
T
STOPH
IICSDA
T
BUF
T
STARTS
T
SDAS
T
SCLHIGH
T
SCLLOW
F
SCL
T
SDAH