Datasheet

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Summary of content (65 pages)

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TM The Samsung ARTIK 530 Module is a highly-integrated ® ® System-in-Module that combines a quad core ARM Cortex -A9 processor packaged DRAM and Flash memories; a Secure Element; and a wide range of wireless communication options ® such as 802.11a/b/g/n, Bluetooth 4.2 (BLE+Classic), and ® 802.15.4 for ZigBee /Thread; all into one 49x36mm footprint. The many standard digital control interfaces support external sensors and higher-performance peripherals to expand the ® module’s capabilities.
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ARTIK 530 Module Table of Contents .................................................................................................................................. 3 List of Figures .......................................................................................................................................................................... 5 List of Tables ............................................................................................................................................
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FCC........................................................................................................................................................................................................ 60 RoHS Compliance ............................................................................................................................................................................... 60 HDMI Compliance ..............................................................................................
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Figure 1. ARTIK 530 Module Functional Block Diagram ......................................................................................................8 Figure 2. ARTIK 530 Module Top View BALL Organization .............................................................................................. 17 Figure 3. ARTIK 530 Module Power Management State Diagram .................................................................................. 38 Figure 4. RF Connector for Bluetooth®/Wi-Fi® and 802.15.
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Table 24. SD/MMC ................................................................................................................................................................. 32 Table 25. SPI ........................................................................................................................................................................... 33 Table 26. UART ..............................................................................................................................
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Revision Date V1.0 January 20, 2017 Description ARTIK 530 datasheet.
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® ® Figure 1 shows the functional block diagram of the ARTIK 530 Module. It consists of a quad-core ARM Cortex -A9 application ® ® processor with 512MB of DDR3 and 4GB eMMC, PMIC power management, Secure Element, Wi-Fi /Bluetooth , 802.15.4 and RF connectors.
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The sub-sections that will follow describe the functions of the various blocks depicted in Figure 1 that are present on the ARTIK 530 Module. The ARTIK 530 Module provides a GPIO system with up to 107 GPIOs (76 multiplexed, 31 dedicated) to allow for a wide variety of use cases to be supported.
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 Slave Mode : Support Tx up to 8MHz, Rx up to 8MHz The ARTIK 530 Module provides three 2-pin universal asynchronous receiver transmitters (UARTs). The key features of the UART sub-system are:      Separate 32x8 Tx and 32x12 Rx FIFO memory buffers Support for DMA mode (UART0 : [AP_UART_RX0, AP_UART_TX0] only) and interrupt based mode of operation All independent channels support IrDA 1.
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 Support for 20 and 40MHz bandwidth (72.2/150Mbps PHY rate) ® ®  Enhanced Wi-Fi /Bluetooth Coexistence control to improve transmission quality in different profiles ® The ARTIK 530 Module has a fully-integrated Bluetooth block 4.2 (BLE+Classic). The most important hardware features of the ® Bluetooth module are: ®  Bluetooth 4.2 (BLE+Classic) ® ®  Enhanced Wi-Fi /Bluetooth Coexistence control to improve transmission quality in different profiles The ARTIK 530 Module carries fully-integrated 802.15.
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 Support for HSIC version 1.0 The ARTIK 530 Module provides one 4-lane mobile industry processor interface (MIPI) interface that complies with the MIPI camera serial interface (CSI) standard specification V1.01r06 and D-PHY standard specification v1.0.
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 MAC supports the following features:  10/100/1000 Mbps data transfer rates with an RGMII interface to communicate with external Gigabit PHY  Full duplex operation  Half duplex operation  Flexible address filtering  Additional frame filtering The ARTIK 530 Module provides one shared SD-card/MMC interface. The Mobile Storage Host is an interface between the system and the SD-card. The key features of mobile storage host sub-system are:       Support for Secure Digital I/O (SDIO – version 3.
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 Embedded tamper-free memory  32KB ROM  264KB FLASH  (6+2.5)KB Static RAM including 2.5KB crypto memory  Serial interfaces:  ISO 7816-3 compliant interface  Asynchronous half-duplex character receive/transmit serial interface The processor system architecture that resides on the ARTIK 530 Module is a system-on-a-chip (SoC) based on a 32-bit RISC architecture. Designed using the 28nm low power process, the processor system architecture provides superior performance using a quad-core CPU.
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 16x DMA request lines  Various operating modes  Single DMA mode  Burst DMA mode  Memory to memory transfer  Memory to peripheral transfer  Peripheral to memory transfer  Peripheral to peripheral transfer  Support for 8/16/32 bit wide transactions  Big endian and little endian (default) support The ARTIK 530 Module has one real time clock (RTC) module. The most important features of the RTC are:     Four spread spectrum PLLs Two external crystals : one 24MHz crystal for PLL, one 32.
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The ARTIK 530 Module provides one 2D and 3D graphics pipeline module.
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The ARTIK 530 Module utilizes 300 signal and ground BALLs providing all the relevant signaling. Figure 2 shows how the BALLs are oriented and how signal coordinates are assigned to the PADs of the ARTIK 530 Module. Table 2, Error! Reference source not found., Table 4 and Table 5 describe the relation between the BALL coordinates and the BALL signal names. Table 2, Error! Reference source not found., Table 4 and Table 5 also provide detailed characteristics for each BALL signal name.
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The meaning of the various columns used in Table 2 - Table 6 is explained in Table 1. Column Name Ball Loc Ball Name Column Definition Identifier of the Ball on the ARTIK 530 Module Default function of the ARTIK 530 Module Power Voltage level on the Ball Default Internal default function of the main SoC I/O Type S=Signal Ball I/O I=Input, O=Output, IO=Input/Output PU/PD PU=Pull-Up, PD=Pull-Down, N=No Pull-Up or Pull-Down Group Default pin group set to work with the Interposer Board.
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Ball Loc Ball Name Power Default PA1 GMAC_TXEN 3V3 GMAC_TXEN I/O Type I/O PU/PD Group S IO N GMAC GMAC Transmit Enable Function PA2 GMAC_TXD1 3V3 GMAC_TXD1 S IO N GMAC GMAC Transmit Data 1 PA3 GMAC_TXD3 3V3 GMAC_TXD3 S IO N GMAC GMAC Transmit Data 3 NA PA4 NO BALL - - - - - NO BALL PA5 GMAC_GTXCLK 3V3 GMAC_GTXCLK S IO N GMAC GMAC Transmit Clock PA6 GMAC_RXDV 3V3 GMAC_RXDV S IO N GMAC GMAC Receive Enable PA7 GMAC_RXD2 3V3 GMAC_RXD2 S IO N GMAC
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Ball Loc Ball Name Power Default PB4 GMAC_MDC 3V3 GMAC_MDC I/O Type I/O PU/PD Group S IO N GMAC Function PB5 GMAC_RXCLK 3V3 GMAC_RXCLK S IO N GMAC GMAX Receive Clock PB6 GMAC_RXD3 3V3 GMAC_RXD3 S IO N GMAC GMAC Receive Data 3 PB7 GMAC_RXD1 3V3 GMAC_RXD1 S IO N GMAC GMAC Receive Data 1 PB8 GMAC_MDIO 3V3 GMAC_MDIO S IO N GMAC GMAC MDIO PB9 GND 0V0 GND NA 0V0 - GND Ground PB10 AP_MIPICSI_DPCLK 1V8 MIPICSI_DPCLK S IO N CSI MIPI CSI Data Positive
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Ball Loc Ball Name Power Default I/O Type I/O PU/PD Group Function PAK1 AP_I2S0_DOUT 3V3 I2SDOUT0 S IO N I2S0 I2S 0 Data Out PAK2 AP_I2S0_BCLK 3V3 I2SBCLK0 S IO N I2S0 I2S 0 Bit Clock PAK3 AP_GPC11_SPI2_MISO 3V3 SA11 S IO N SPI2 SPI 2 Receive Data PAK4 AP_GPC9_SPI2_CLK 3V3 SA9 S IO N SPI2 SPI 2 Clock PAK5 AP_SPI0_MISO 3V3 SPIRXD0 S IO N SPI0 SPI 0 Receive Data PAK6 AP_SPI0_CLK 3V3 SPICLK0 S IO N SPI0 SPI 0 Clock PAK7 AP_GPC14_PWM2 3V3 SA14 S
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Ball Loc Ball Name Power Default I/O Type I/O PU/PD Group Function PAL6 AP_SPI0_CS 3V3 SPIFRM0 S IO N SPI0 SPI 0 Frame PAL7 AP_GPD1_PWM0 3V3 PWM0 S IO N PWM PWM 0 PAL8 AP_GPD7_SDA2 3V3 SDA2 S IO N I2C I2C SDA I2C SDA 1 PAL9 AP_GPD5_SDA1 3V3 SDA1 S IO N I2C PAL10 AP_GPD3_SDA0 3V3 SDA0 S IO N I2C I2C SDA 0 PAL11 AP_GPA24_HDMI_I2C_SDA 3V3 DISD23 S IO N I2C HDMI I2C SDA PAL12 ZB_DEBUG_TMS_SWDIO 3V3 - - - - 802.15.4 802.15.
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Ball Loc Ball Name Power Default I/O Type I/O PU/PD Group Function PC1 GND 0V0 GND NA 0V0 - GND Ground PC2 NO BALL - - - - - NO BALL NA PD1 GND 0V0 GND NA 0V0 - GND Ground PD2 NO BALL - - - - - NO BALL NA PE1 GND 0V0 GND NA 0V0 - GND Ground PE2 GND 0V0 GND NA 0V0 - GND Ground PF1 GND 0V0 GND NA 0V0 - GND Ground PF2 GND 0V0 GND NA 0V0 - GND Ground PG1 GND 0V0 GND NA 0V0 - GND Ground PG2 NO BALL - - - - - NO BALL
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Ball Loc Ball Name Power Default I/O Type I/O PU/PD Group PAG1 AP_NRESET 3V3 NRESET S I PU KEY Function Reset PAG2 AP_GPA25_BACKKEY 3V3 DISVSYNC S IO N KEY Back Key PAH1 AP_GPA26_VOLUP 3V3 DISHSYNC S IO N KEY Volume Up PAH2 AP_GPA0_MENUKEY 3V3 DISCLK S IO N KEY Menu Key PAJ1 AP_I2S0_LRCLK 3V3 I2SLRCLK0 S IO N I2S0 I2S 0 Left Right Clock PAJ2 AP_GPA27_VOLDOWN 3V3 DISDE S IO N KEY Volume Down 24
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Ball Loc Ball Name Power Default I/O Type I/O PU/PD Group Function PC39 GND 0V0 GND NA 0V0 - GND Ground PC40 GND 0V0 GND NA 0V0 - GND Ground PC41 GND 0V0 GND NA 0V0 - GND Ground PC42 GND 0V0 GND NA 0V0 - GND Ground PD41 VCC5P0_OTGVB US - - NA 5V0 - POWER USB2.0 OTG BUS Power PD42 VCC5P0_OTGVB US - - NA 5V0 - POWER USB2.
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Ball Loc Ball Name Power Default I/O Type I/O PU/PD Group Function PAE41 GND 0V0 GND NA 0V0 - GND Ground PAE42 NC - - - - - NC - PAF41 GND 0V0 GND NA 0V0 - GND Ground PAF42 GND 0V0 GND NA 0V0 - GND Ground PAG41 AP_GPB11 3V3 CLE0 S IO N GPIO Generic GPIO PAG42 AP_GPB18 3V3 NNFWE0 S IO N GPIO Generic GPIO PAH41 AP_GPC25 3V3 NSWAIT S IO PU GPIO Generic GPIO PAH42 AP_GPE31 3V3 NSWE S IO PU GPIO Generic GPIO PAJ39 BT_PCM_CLK 3V3
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This section shows the functional interfaces that are available at the PADs of the ARTIK 530 Module. The functions provided are related to the development environment used. Depending on your project you can always choose to reprogram some of the GPIOs that are currently assigned to the pre-defined functional interfaces.
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Ball Loc Ball Name Power Default I/O Type I/O PU/PD Function S IO N MIPI DSI Data Negative Clock PA16 AP_MIPIDSI_DNCLK 1V8 MIPIDSI_DNCL K PA17 AP_MIPIDSI_DN0 1V8 MIPIDSI_DN0 S IO N MIPI DSI Data Negative 0 PA18 AP_MIPIDSI_DN1 1V8 MIPIDSI_DN1 S IO N MIPI DSI Data Negative 1 PA19 AP_MIPIDSI_DN2 1V8 MIPIDSI_DN2 S IO N MIPI DSI Data Negative 2 PA20 AP_MIPIDSI_DN3 1V8 MIPIDSI_DN3 S IO N MIPI DSI Data Negative 3 S IO N MIPI DSI Data Positive Clock PB16 AP_MIPID
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Ball Loc Ball Name Power Default I/O Type I/O PU/PD Function PA37 AP_GPA13 3V3 DISD12 S IO N Generic GPIO PA39 AP_GPA14 3V3 DISD13 S IO N Generic GPIO PA40 AP_GPA9 3V3 DISD8 S IO N Generic GPIO PA41 AP_GPA15 3V3 DISD14 S IO N Generic GPIO PA42 AP_GPA12 3V3 DISD11 S IO N Generic GPIO PB39 AP_GPA4 3V3 DISD3 S IO N Generic GPIO PB40 AP_GPA5 3V3 DISD4 S IO N Generic GPIO PB41 AP_GPA16 3V3 DISD15 S IO N Generic GPIO PB42 AP_GPA11 3V3 DISD
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Ball Loc Ball Name Power Default PU/PD Function PA38 AP_HSIC_STROBE 1V2 USBHSIC_STROBE I/O Type I/O S IO N HSIC Strobe PB38 AP_HSIC_DATA 1V2 USBHSIC_DATA S IO N HSIC Data Ball Loc Ball Name Power Default I/O Type I/O PU/PD PAK8 AP_GPD6_SCL2 3V3 SCL2 S IO N Function I2C SCL PAK9 AP_GPD4_SCL1 3V3 SCL1 S IO N I2C SCL 1 PAK10 AP_GPD2_SCL0 3V3 SCL0 S IO N I2C SCL 0 PAK11 AP_GPA23_HDMI_I2C_SCL 3V3 DISD22 S IO N HDMI I2C SCL PAL8 AP_GPD7_SDA2 3V3 SDA2
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Ball Loc Ball Name Power Default I/O Type I/O PU/PD Function PAE2 AP_AGP2_RTC_INT_N 3V3 ALIVEGPIO2 S IO N Left Key part of AliveGPIO PAF1 AP_PWRKEY 3V3 ALIVEGPIO0 S IO N Power Key part of AliveGPIO PAF2 AP_AGP1_HOMEKEY 3V3 ALIVEGPIO1 S IO N Home Key part of AliveGPIO PAG1 AP_NRESET 3V3 NRESET S I PU Reset PAG2 AP_GPA25_BACKKEY 3V3 DISVSYNC S IO N Back Key PAH1 AP_GPA26_VOLUP 3V3 DISHSYNC S IO N Volume Up PAH2 AP_GPA0_MENUKEY 3V3 DISCLK S IO N Me
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Ball Loc Ball Name Power Default I/O Type I/O PU/PD Function PAK17 VCC3P3_SYS* 3V3 - NA 3V3 - POWER PAK18 VCC3P3_SYS* 3V3 - NA 3V3 - POWER PAL17 VCC3P3_SYS* 3V3 - NA 3V3 - POWER PAL18 VCC3P3_SYS* 3V3 - NA 3V3 - POWER PD41 VCC5P0_OTGVBUS - - NA 5V0 - POWER PD42 VCC5P0_OTGVBUS - - NA 5V0 - POWER PV41 VBAT_MAIN VBAT - NA - POWER PV42 VBAT_MAIN VBAT - NA - POWER PW41 VBAT_MAIN VBAT - NA - POWER PW42 VBAT_MAIN VBAT - NA - POWER P
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Ball Loc Ball Name Power Default I/O Type I/O PU/PD Function PAK3 AP_GPC11_SPI2_MISO 3V3 SA11 S IO N SPI 2 Receive Data PAK4 AP_GPC9_SPI2_CLK 3V3 SA9 S IO N SPI 2 Clock PAK5 AP_SPI0_MISO 3V3 SPIRXD0 S IO N SPI 0 Receive Data PAK6 AP_SPI0_CLK 3V3 SPICLK0 S IO N SPI 0 Clock PAL3 AP_GPC12_SPI2_MOSI 3V3 SA12 S IO N SPI 2 Transmit Data PAL4 AP_GPC10_SPI2_CS 3V3 SA10 S IO PU SPI 2 Frame PAL5 AP_SPI0_MOSI 3V3 SPITXD0 S IO N SPI 0 Transmit Data PAL6 A
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A number of the GPIOs can be programmed to have alternate functions beyond their default behavior using the GPIO API provided in the SW development environment. Table 29, Table 30, Table 31 and Table 32 provide the alternate functions of all the GPIOs that are available on the PADs of the ARTIK 530 Module that can be user programmed.
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GPIO Alternate Functions SOUTH PART Ball Loc Ball Name Default Function PAK1 AP_I2S0_DOUT I2SDOUT0 PAK2 AP_I2S0_BCLK I2SBCLK0 PAK3 AP_GPC11_SPI2_MISO PAK4 PAK5 I/O Function 0 Function 1 Function 2 Function 3 Group IO GPIOD9 I2SDOUT0 AC97_DOUT - I2S0 IO GPIOD10 I2SBCLK0 AC97_BCLK - I2S0 GPIOC11 SPIRXD2 USB2.
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GPIO Alternate Functions SOUTH PART Ball Loc Ball Name Default Function I/O Function 0 Function 1 Function 2 Function 3 Group PAL21 AP_GPE0 VID0_4 IO GPIOE0 VID0_4 TSIDATA1_4 - MISC PAL22 AP_UART_RX3 UARTRXD3 IO GPIOD17 UARTRXD3 - - UART PAL23 AP_UART_RX4 SD12 IO SD12 GPIOB28 TSIDATA0_4 UARTRXD4 UART PAL24 AP_UART_RX0 UARTRXD0 IO GPIOD14 UARTRXD0 ISO7816 - UART PAL25 AP_GPD31 VID0_3 IO GPIOD31 VID0_3 TSIDATA1_3 - MISC PAL26 AP_GPB9_I2SDIN1 VID1_6 IO
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The ARTIK 530 Module supports a variety of booting scenarios as depicted in Table 33. Table 34 describes the values of the PAD signals needed to initiate the various booting scenarios. When nothing is done default booting will take place. (AP_GPB13_SD0_BOOT is High, AP_GPB15_SD1_BOOT is Low and AP_GPB4_VID1_3_BOOT is High) In this case the ARTIK 530 Module will try to boot from eMMc, if this fails it will continue to initiate a boot from SD0 and if this fails it will continue booting from the USB device.
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Figure 3 shows the Power Management state diagram. In this diagram the entry and WAKEUP conditions for each power down mode are given.
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Two antennas are required to use the full set of radio communication links on the ARTIK 530 Module. One supports the ® ® combination of Wi-Fi /Bluetooth , and the other is dedicated to 802.15.4. Caution: Do not apply power (enable) the radio chips before connecting antennas or damage to the chip may result. All Dimensions are in mm ® ® The U.FL-R-SMT Hirose connector is used for both the Bluetooth /Wi-Fi and the 802.15.4 (ZigBee/Thread) antenna connectors on the ARTIK 530 Module.
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The ratings given in this section are associated only with stress. It does not imply any functional operation of the device. Exposure to the absolute-maximum rated conditions for long duration affects the reliability of the device. Absolute Maximum Ratings Parameter Symbol Condition Min Max Main battery supply VBAT_MAIN – -0.3 6.0 3.3V Buffer -0.5 3.8 5V Tolerant buffer -0.3 5.3 PAK:[15] PAL:[15] Non 5V Tolerant Buffer -0.3 3.6 PAL:[19] PAF:[1] PAG:[1] – -0.3 3.
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The recommended operation of the ARTIK 530 Module is based on the operating conditions listed in Table 36. Table 36. Recommended Operating Conditions Parameter Symbol Min Typ Max Units Main Battery Supply VBAT_MAIN PV:[41,42],PW:[41,42],PY:[41,42],PAA:[4 1,42],PAB:[41,42] 3.7 4.20 5.
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The power management of the ARTIK 530 Module as described in Figure 5 is controlled by a PMIC. This PMIC contains four high efficiency DC-DC converters and five LDO regulators. See Table 37 and Table 38 for details on voltage and amperage ranges and how they are used in the ARTIK 530 Module. Buck Powers Header Max Current [mA] Range [V] Default [V] DCDC1 ARM of Main SoC – 3000 0.60-3.50 DCDC2 Core of Main SoC – 3000 0.60-3.50 1.0 DCDC3 DDR3 IO Memory – 2000 0.60-3.50 1.
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LDO Powers Header Current [mA] Range [V] Step [mV] Default [V] LDO1 Main SoC :[IO,USB,USBHOST,VIDEO,GMAC] – 300 0.90-3.50 50 – LDO2 Wi-Fi®/Bluetooth®, Main SoC:[ADC,PLL] – 300 0.90-3.50 50 – LDO3 FLASH, Wi-Fi®/Bluetooth®, 802.15.4, Main SoC:[USB OTG] PAK:[17,18],PAL:[17,18] 300 0.90-3.50 50 3.30 LDO4 Main SoC:[HSIC] – 200 0.90-3.50 50 1.20 LDO5 Not Used – – – – – PAK:[17,18],PAL:[17,18] Operating Conditions VIN=3.
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Symbol Min. Max.
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The DC characteristics for the GPIO pins of the ARTIK 530 Module are listed in Table 42. Use the parameters from Table 42 to determine maximum DC loading and to determine maximum transition times for a given load. VDD = 3.3V, Vext = 3.0 to 3.6 V, TJ = -25 to 85 °C (TJ = Junction Temperature), 3.
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802.15.4 BALL Coordinates Symbol Description Condition Min Typ Max IOH High Level Output Current Push-Pull & PMOS OD, VOH=2.4V, 1x Driver at VDD=3.3V 5.774 11.066 – IOL Low Level Output Current Push-Pull, VOL=0.4V, 1x Driver at VDD=3.3V 4.491 6.
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AC characteristics covered in this section are preliminary and are likely to change. HS_SDCLK tHSDCD HS_SDCMD (out) tHSDCS tHSDCH HS_SDCMD (in) tHSDDD HS_SDDATA[7:0] (out) tHSDDS tHSDDH HS_SDDATA[7:0] (in) (VDDINT = 1.0V  5%, TJ = -25 to 85C, VDDmmc = 3.3V  5 %, 2.5V  5%, 1.8V  5%) BOT:[59,60,61,62,63,64] Symbol Parameter Min Typ Max tSDCD SD command output delay time – – 4.0 tSDCS SD command input setup time 4.
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SPICLK XspiMOSI (MO) tSPIMIH tSPIMOD XspiMISO (MI) tSPIMIS XspiMISO (SO) tSPISOD tSPISIH XspiMOSI (SI) tSPISIS XspiCS tSPICSSD tSPICSSS 48
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(VDDINT = 1.0 V  5 %, TJ = -25 to 85 C, VDDext = 1.
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(VDDINT = 1.0 V  5 %, TJ = –25 to 85C, VDDext = 3.
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FSCL TSCLHIGH TSCLLOW IICSCL TSTOPH TBUF TSDAS TSDAH TSTARTS IICSDA 2 I C BUS Controller Module Signal Timing (VDDINT, VDDarm = 1.1 V ± 5 %, TJ = -25 to 85°C, VDDext = 3.3 V ± 10 %) Parameter Symbol SCL clock frequency SCL high level pulse width SCL low level pulse width Bus free time between STOP and START START hold time SDA hold time SDA setup time STOP setup time Min. Typ. Max. Unit kHz FSCL – – std. 100 fast 400 TSCLHIGH std. 4.0 fast 0.6 – – TSCLLOW std. 4.7 fast 1.
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® ® All performance numbers related to Wi-Fi /Bluetooth and 802.15.4 mentioned in this section are preliminary and likely to change once module characterization has taken place. Parameter Frequency Range Conditions – Min Typ. Max Unit 2400 – 2500 MHz Minimum receiver sensitivity in 802.11b mode (2.4GHz) 1Mbps 2Mbps 5.5Mbps PER < 8%, Packet size = 1024 bytes 11Mbps – -97 – dBm – -95 – dBm – -94 – dBm – -90 – dBm Minimum receiver sensitivity in 802.11g mode (2.
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Parameter Conditions Min Typ. Max Unit – 15 – dBm – 15 – dBm – 13 – dBm 0 – – dBr 0 – – dBr 0 – – dBr – – 35 % – – 35 % – – 35 % – – 35 % 6Mbps – – -5 dB 9Mbps – – -8 dB 12Mbps – – -10 dB – – -13 dB – – -16 dB 36Mbps – – -19 dB 48Mbps – – -22 dB 54Mbps – – -25 dB – – -27 dB Linear output power Maximum output power in 802.11b mode Maximum output power in 802.11g mode Maximum output power in 802.
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Parameter Conditions Min Typ. Max Unit Frequency Range – 4900 – 5845 MHz Minimum receiver sensitivity in 802.11a mode 6Mbps – -90 – dBm 9Mbps – -89 – dBm 12Mbps – -88 – dBm 18Mbps – -87 – dBm – -84 – dBm 36Mbps – -80 – dBm 48Mbps – -76 – dBm 54Mbps – -75 – dBm PER < 10% 24Mbps Minimum receiver sensitivity in 802.
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Parameter Frequency Range Sensitivity (BER) Maximum Input Level Conditions Min Typ Max Unit – 2402 – 2480 MHz GPSK, BER ≤0.1% – –92 – dBm π/4-DQPSK, BER ≤ 0.1% – –92 – dBm BER ≤ 0.1%, 8DPSK – –89 – dBm GPSK, BER ≤0.1% -20 – – dBm π/4-DQPSK, BER ≤ 0.1% -20 – – dBm BER ≤ 0.1%, 8 DPSK -20 – – dBm BDR Intermodulation Performance – – – 0.1 % 1DH1 – – 0.1 % 1DH3 – – 0.1 % 1DH5 – – 0.1 % 2DH1 – – 0.1 % 2DH3 – – 0.1 % 2DH5 – – 0.
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The Typ numbers indicated in Table 59 and Table 60 are one standard deviation below the mean, measured at room temperature 25°C. The Min and Max numbers were measured over process corners at room temperature. Parameter Test Condition Min Typ Max Unit MHz Operating Frequency Range – 2400 – 2483.
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The ARTIK 530 Module supports PAD Balls and two RF connectors on a 49mm x 36mm footprint as shown in Figure 9. Refer to section Antenna Connections for RF connector details. In addition the top view, side view and bottom view with its dimensions can be seen in Figure 10 and Figure 11.
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The inner pin locations on the PAD, positioned in an L-shaped form, as depicted in Figure 12, are located in Table 61. The inner PAD’s are on a different grid from the outer PAD’s as indicated with the dashed blue lines in Figure 12. For exact dimensions on location see Figure 11. The locations given in Table 61 are the absolute coordinates measured from the edge of the ARTIK 530 Module to the center of each ball.
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® The ARTIK 530 Module is recognized as a qualified design as set out by Bluetooth SIG. Declaration ID: D032725 Qualified Design ID: 88390 The ARTIK 530 Module is in compliance with each applicable article of the R&TTE directive. Compliance with the following standards was confirmed:     LVD: EN60950-1 (2006+A11, 2009+A1, 2010+A12, 2011+A2, 2013) EMF: EN62311:2008 EMC: 301 489-1 V1.9.2, EN 301 489-17 V2.2.
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This device complies with Part 15 of the FCC`s Rules. Operation is subject to the following two Conditions: (1) This device may not cause harmful interference, and (2) This device must accept any interference received, including interference that may cause undesirable operation. This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules.
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This device complies with Industry Canada license-exempt RSS standard(s). Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. Cet appareil est conforme avec Industrie Canada exempts de licence standard RSS (s).
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The following statement must be supplied with each product but can be printed in the user manual, the packaging, or provided as a separated leaflet. Hereby, Samsung declares that this IoT Module is in compliance with the essential requirements and other relevant provisions of Article 3 of the R&TTE Directive 1999/5/EC, 2004/108/EC and RoHS directive 2011/65/EU. “The declaration of conformity may be consulted at [www.artik.
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Please contact a sales representative in your area using the ARTIK official webpage – http://www.artik.
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INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH THE SAMSUNG ARTIK™ DEVELOPMENT KIT AND ALL RELATED PRODUCTS, UPDATES, AND DOCUMENTATION (HEREINAFTER “SAMSUNG PRODUCTS”). NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT.