Datasheet

Mechanical and electrical specifications LIS3DH
14/54 DocID17530 Rev 2
2.4.2 I
2
C - Inter IC control interface
Subject to general operating conditions for Vdd and top.
Figure 4. I
2
C slave timing diagram
Note: Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both ports.
Table 8. I
2
C slave timing values
Symbol Parameter
I
2
C standard
1. Data based on standard I
2
C protocol requirement, not tested in production.
I
2
C fast mode
(1)
Unit
Min Max Min Max
f
(SCL)
SCL clock frequency 0 100 0 400 kHz
t
w(SCLL)
SCL clock low time 4.7 1.3
μs
t
w(SCLH)
SCL clock high time 4.0 0.6
t
su(SDA)
SDA setup time 250 100 ns
t
h(SDA)
SDA data hold time 0 3.45 0 0.9 μs
t
h(ST)
START condition hold time 4 0.6
μs
t
su(SR)
Repeated START condition setup time 4.7 0.6
t
su(SP)
STOP condition setup time 4 0.6
t
w(SP:SR)
Bus free time between STOP and
START condition
4.7 1.3
SD A
SCL
t
su(SP)
t
w(SCLL)
t
su(SDA)
t
su(SR)
t
h(ST)
t
w(SCLH)
t
h(SDA)
t
w(SP:SR)
START
REP EA T ED
STA RT
STOP
STA RT