Datasheet

DocID17530 Rev 2 13/54
LIS3DH Mechanical and electrical specifications
54
2.4 Communication interface characteristics
2.4.1 SPI - serial peripheral interface
Subject to general operating conditions for Vdd and Top.
Figure 3. SPI slave timing diagram
1. When no communication is ongoing, data on SDO is driven by internal pull-up resistors.
Note: Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both input and output
ports.
Table 7. SPI slave timing values
Symbol Parameter
Value
(1)
Unit
Min Max
t
c(SPC)
SPI clock cycle 100 ns
f
c(SPC)
SPI clock frequency 10 MHz
t
su(CS)
CS setup time 5
ns
t
h(CS)
CS hold time 20
t
su(SI)
SDI input setup time 5
t
h(SI)
SDI input hold time 15
t
v(SO)
SDO valid output time 50
t
h(SO)
SDO output hold time 5
t
dis(SO)
SDO output disable time 50
1. Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not
tested in production.
SPC
CS
SD I
SD O
t
su(CS)
t
v(SO)
t
h(SO)
t
h(SI)
t
su(SI)
t
h(CS)
t
dis(SO)
t
c(SPC)
MSB IN
MSB OUT
LSB OUT
LSB IN
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)