Datasheet

Short form data sheet Rev. 1.2 — 31 March 2011 9 of 25

Philips Semiconductors

PN532/C1

NFC controller

9.1.1 Simplify block diagram

The Analog interface handles the modulation and demodulation of the analog signals

according to the card receiving mode, reader / writer mode and NFCIP-1 mode

communication scheme.

The RF level detector detects the presence of an external RF-field delivered by the

antenna to the RX pin.

The data mode detector detects a MIFARE

, FeliCa™ or NFCIP-1 mode in order to

prepare the internal receiver to demodulate signals, which are sent to the PN512.

The communication (S2C) interface provides digital signals to support communication for

transfer speeds above 424 kbit/s and digital signals to communicate to a secure core IC.

The contactless UART handles the protocol requirements for the communication schemes

in co-operation with the host. The comfortable FIFO buffer allows a fast and convenient

data transfer from the host to the contactless UART and vice versa.

9.1.2 Feature list

• Close communication link to the analog circuitry to demodulate and decode card’s

response

• Typical MOVX access to non critical registers

• SFR register map for high frequency register access (16 Registers)

• Integrated data mode detector

• Supports ISO 14443A / MIFARE

• Supports ISO 14443 B reader / writer functionality

• Adjustable parameters to optimize the reception according to the antenna

configuration

• Adjustable parameters to optimize the transmisssion according to the antenna

configuration and characteristics.

• typical operating distance in reader / writer mode for communication to a ISO 14443A/

MIFARE

or FeliCa™ card up to 50 mm depending on the antenna size, tuning and

power supply

Fig 2. Memory manager shift register management.