Datasheet

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Short form data sheet Rev. 1.2 — 31 March 2011 6 of 25
Philips Semiconductors
PN532/C1
NFC controller
8. Pinning information
8.1 Pin description
Table 3: PN532 Pin description
Symbol Pin Type Pad Ref
Voltage
Description
DVSS 1 PWR Digital Ground
LOADMOD 2 O DVDD Load Modulation output provides digital signal for FeliCa™ and MIFARE
®
card operating mode
TVSS1 3 PWR Transmitter Ground: supplies the output stage of TX1 and TX2
TX1 4 O TVDD Transmitter 1: delivers the modulated 13.56 MHZ energy carrier
TVDD 5 PWR Internal Transmitter power supply: supplies the output stage of TX1 and TX2
TX2 6 O TVDD Transmitter 2: delivers the modulated 13.56 MHZ energy carrier
TVSS2 7 PWR Transmitter Ground: supplies the output stage of TX1 and TX2
AVDD 8 PWR Internal Analog Power Supply
VMID 9 O AVDD Internal Reference Voltage: This pin delivers the internal reference voltage.
RX 10 I AVDD Receiver Input: Input pin for the reception signal, which is the load modulated
13.56 MHZ energy carrier from the antenna circuit.
AVSS 11 PWR Analog Ground
AUX1 12 O AVDD Auxiliary Output: This pin delivers analog and digital test signals.
AUX2 13 O AVDD Auxiliary Output: This pin delivers analog and digital test signals.
OSCIN 14 I AVDD Crystal Oscillator Input: input to the inverting amplifier of the oscillator.This
pin is also the input for an externally generated clock (fosc = 27.12 MHZ).
OSCOUT 15 O AVDD Crystal Oscillator output: Output of the inverting amplifier of the oscillator.
I0 16 I DVDD General purpose IO signal
Can be used by the embedded firware to select the used host interface.
I1 17 I DVDD General purpose IO signal
Can be used by the embedded firware to select the used host interface.
TESTEN 18 I DVDD Test enable pin:
When set to 1 enable the test mode.
When set to 0 reset the TCB and disable the access to the test mode.
P35 19 IO DVDD General purpose IO signal
NC 20
NC 21
NC 22
PVDD 23 PWR Pad power supply
P30 24 IO PVDD General purpose IO signal. Can be configured to act either as RX line of the
second serial interface or general purpose IO.
In test mode this signal is used as input and output test signal.
IRQ 25 O PVDD Interrupt request: Output to signal an interrupt event to the host (Port 7 bit 0)
RSTOUTN 26 IO PVDD Output reset signal. When Low it indicates that the circuit is in reset state.
NSS 27 IO PVDD Not Slave Select .
MOSI 28 IO PVDD Master Out Slave In.
MISO 29 IO PVDD Master In Slave Out .
SCK 30 IO PVDD