Datasheet

Beijing Winner Microelectronics Co., Ltd.

⚫ Support soft reset;

⚫ Support SPI, 1bit SD mode and 4 bits SD mode;

6.2 High speed SPI Controller

Support SPI protocol, has configurable data frame. The maximum data rate is 50Mbp.

⚫ Support SPI protocol;

⚫ Support alternative interrupt signal;

⚫ Support max data rate 50Mbps;

⚫ hardware decode and DMA data transfer;

6.3 DMA Controller

Support 8 channel, 16 DMA request signals, has chain table and register configuration.

⚫ Support Amba2.0 protocol, 8 DMA channel;

⚫ Support chain table operating mode;

⚫ 16 configurable DMA request signals;

⚫ Support 1,4-burst data transfer;

⚫ Support byte-, half-word-, word- access;

⚫ Programmable source or destination address unchanged, sequentially increases or pre-defined;

⚫ Synchronous DMA request and DMA response timing;

6.4 Clock and Reset Controller

Support the control of clock and reset system. Clock control includes clock frequency conversion, clock turn

off and adaptive gating, and reset control includes soft reset control of system and sub modules.

6.5 Memory Controller

Support the cache size configuration during transmitting and receiving, MAC access base address, cache

number and frame aggregation control signals.

6.6 BBP

Support IEEE802.11a/b/g/e/n (1T1R). The main features are:

⚫ Data rate: 1~54Mpbs (802.11a/b/g), 6.5~150Mbps (802.11n);

⚫ MCS data format：MCS0~MCS7,MCS32(40MHz HT Duplicate mode);

⚫ Support 40MHz bandwidth non-HT Duplicate mode, 6M～54M;

⚫ Signal bandwidth：20MHz, 40MHz;

⚫ Modulation mode：DSSS(DBPSK,DQPSK,CCK) and OFDM(BPSK,QPSK,16QAM,64QAM);