ESP8285 Datasheet Version 1.
About This Guide This document introduces the specifications of ESP8285, including the following topics: Chapter Title Subject Chapter 1 Overview Provides an overview of ESP8285, including features, protocols, technical parameters and applications. Chapter 2 Pin Definitions Provides the pin layout and the relevant description. Chapter 3 Functional Description Describes major functional modules integrated on ESP8285 including CPU, flash and memory, clock, radio, Wi-Fi, and low-power management.
Table of Contents 1. Overview ................................................................................................................................ 1 1.1. Wi-Fi Protocol...........................................................................................................................1 1.2. Main Technical Specifications .................................................................................................. 3 1.3. Applications......................................................
.10. LED Light and Button .............................................................................................................18 5. Electrical Specifications ......................................................................................................19 5.1. Electrical Characteristics ........................................................................................................19 5.2. Power Consumption.............................................................................
1. Overview $ 1. Overview Espressif’s ESP8285 delivers highly integrated Wi-Fi SoC solution to meet users’ continuous demands for efficient power usage, compact design and reliable performance in the Internet of Things industry. With the complete and self-contained Wi-Fi networking capabilities, ESP8285 can perform either as a standalone application or as the slave to a host MCU. When ESP8285 hosts the application, it promptly boots up from the flash.
1. Overview $ • WMM power save U-APSD. • Multiple queue management to fully utilize traffic prioritization defined by 802.11e standard. • UMA compliant and certified. • 802.1h/RFC1042 frame encapsulation. • Scattered DMA for optimal CPU off load on Zero Copy data transfer operations. • Antenna diversity and selection (software managed hardware). • Clock/power gating combined with 802.11-compliant power management dynamically adapted to current connection condition providing minimal power consumption.
1. Overview $ 1.2. Main Technical Specifications Table 1-1. Main Technical Specifications Categories Items Parameters Standards FCC/CE/TELEC/SRRC Protocols 802.11 b/g/n/e/i Frequency Range 2.4G ~ 2.5G (2400M ~ 2483.5M) 802.11 b: +20 dBm Wi-Fi Tx Power 802.11 g: +17 dBm 802.11 n: +14 dBm 802.11 b: -91 dbm (11 Mbps) Rx Sensitivity 802.11 g: -75 dbm (54 Mbps) 802.
1. Overview $ 1.3. Applications Espressif • Home Appliances • IP Cameras • Home Automation • Sensor Networks • Smart Plugs and Lights • Wearable Electronics • Mesh Network • Wi-Fi Location-aware Devices • Industrial Wireless Control • Security ID Tags • Baby Monitors • Wi-Fi Position System Beacons $ /$25 4 2017.
2. Pin Definitions $ 2. Pin Definitions Figure 2-1 shows the pin layout for 32-pin QFN package. ! Figure 2-1. Pin Layout Table 2-1 lists the definitions and functions of each pin. Table 2-1. ESP8285 Pin Definitions Pin Name Type Function 1 VDDA P Analog Power 2.5V ~ 3.6V RF Antenna Interface. Chip Output Impedance=39+j6Ω 2 LNA I/O 3 VDD3P3 P Amplifier Power 2.5V ~ 3.6V 4 VDD3P3 P Amplifier Power 2.5V ~ 3.6V 5 VDD_RTC P NC (1.1V) I ADC pin.
2. Pin Definitions $ Pin Name Type Function 8 XPD_DCDC I/O Deep-sleep wakeup (need to be connected to EXT_RSTB); GPIO16. 9 MTMS I/O GPIO14; HSPI_CLK 10 MTDI I/O GPIO12; HSPI_MISO 11 VDDPST P Digital/IO Power Supply (1.8V ~ 3.3V) 12 MTCK I/O GPIO13; HSPI_MOSI; UART0_CTS 13 MTDO I/O GPIO15; HSPI_CS; UART0_RTS 14 GPIO2 I/O UART Tx during flash programming; GPIO2 15 GPIO0 I/O GPIO0; SPI_CS2 16 GPIO4 I/O GPIO4 17 VDDPST P Digital/IO Power Supply (1.8V ~ 3.
3. Functional Description $ 3. Functional Description The functional diagram of ESP8285 is shown as in Figure 3-1. RF receive MAC Analog receive PMU Analog transmit VCO 1/2 Crystal Digital baseband RF transmit PLL UART GPIO Switch RF balun Registers Interface I2C I2S Sequencers SDIO PWM Accelerator PLL Bias circuits CPU ADC SPI SRAM PMU Flash $ Figure 3-1. Functional Block Diagram 3.1. CPU, Memory, and Flash 3.1.1.
3. Functional Description $ • RAM size < 50 kB, that is, when ESP8285 is working under the Station mode and connects to the router, programmable space accessible in heap + data section is around 50 kB. • There is no programmable ROM in the SoC, therefore, user program must be stored in a SPI flash. 3.1.3. Flash ESP8285 has a built-in SPI flash to store user programs. • Memory size: 1 MB • SPI mode: Dual Out 3.2. AHB and AHB Blocks The AHB block performs as an arbiter.
3. Functional Description $ Parameter Symbol Min Max Unit Motional capacitance CM 2 5 pF Series resistance RS 0 65 Ω Frequency tolerance ΔFXO -15 15 ppm Frequency vs. temperature (-25°C ~ 75°C) ΔFXO,Temp -15 15 ppm 3.3.2. External Clock Requirements An externally generated clock is available with the frequency ranging from 24 MHz to 52 MHz. The following characteristics are expected to achieve good performance of radio. Table 3-2.
3. Functional Description $ Channel No. Frequency (MHz) Channel No. Frequency (MHz) 3 2422 10 2457 4 2427 11 2462 5 2432 12 2467 6 2437 13 2472 7 2442 14 2484 3.4.2. 2.4 GHz Receiver The 2.4-GHz receiver down-converts the RF signals to quadrature baseband signals and converts them to the digital domain with 2 high resolution high speed ADCs.
3. Functional Description $ distributed control function (DCF) but also P2P group operation compliant with the latest Wi-Fi P2P protocol. Low level protocol functions are handled automatically by ESP8285. • RTS/CTS • acknowledgement • fragmentation and defragmentation • aggregation • frame encapsulation (802.
3. Functional Description $ • Off: CHIP_PU pin is low. The RTC is disabled. All registers are cleared. • Deep-sleep: Only RTC is powered on—the rest of the chip is powered off. Recovery memory of RTC can keep basic Wi-Fi connecting information. • Sleep: Only the RTC is operating. The crystal oscillator is disabled. Any wake-up events (MAC, host, RTC timer, external interrupts) will put the chip into the wake up mode. • Wake up: In this state, the system switches from the sleep states to the PWR mode.
4. Peripheral Interface $ 4. Peripheral Interface 4.1. General Purpose Input/Output Interface (GPIO) ESP8285 has 17 GPIO pins which can be assigned to various functions by programming the appropriate registers. Each GPIO can be configured with internal pull-up or pull-down, or set to high impedance, and when configured as an input, the data are stored in software registers; the input can also be set to edge-trigger or level trigger CPU interrupts.
4. Peripheral Interface $ 4.3. Serial Peripheral Interface (SPI/HSPI) ESP8285 has 3 SPIs. • One general Slave/Master SPI • One Slave SDIO/SPI • One general Slave/Master HSPI Functions of all these pins can be implemented via hardware. The pin definitions are described as below. 4.3.1. General SPI (Master/Slave) Table 4-2.
4. Peripheral Interface $ Table 4-4. Pin Definitions of I2C Pin Name Pin Num IO Function Name MTMS 9 IO14 I2C_SCL GPIO2 14 IO2 I2C_SDA Both I2C Master and I2C Slave are supported. I2C interface functionality can be realized via software programming, the clock frequency reaches 100 kHz at a maximum. It should be noted that I2C clock frequency should be higher than the slowest clock frequency of the slave device. 4.5.
4. Peripheral Interface $ Table 4-6. Pin Definitions of UART Pin Type Pin Name Pin Num IO Function Name U0RXD 25 IO3 U0RXD U0TXD 26 IO1 U0TXD MTDO 13 IO15 U0RTS MTCK 12 IO13 U0CTS GPIO2 14 IO2 U1TXD SD_D1 23 IO8 U1RXD UART0 UART1 Data transfers to/from UART interfaces can be implemented via hardware. The data transmission speed via UART interfaces reaches 115200 x 40 (4.5 Mbps). UART0 can be used for communication. It supports flow control.
4. Peripheral Interface $ frequency is 1 kHz, the duty ratio will be 1/22727, and a resolution over 14 bits will be achieved at 1 kHz refresh rate. 4.8. IR Remote Control One Infrared remote control interface is defined as below. Table 4-8. Pin Definitions of IR Remote Control Pin Name Pin Num IO Function Name MTMS 9 IO14 IR Tx GPIO5 24 IO5 IR Rx The functionality of Infrared remote control interface can be implemented via software programming.
4. Peripheral Interface $ The value of the 107th byte of esp_init_data_default.bin (0 ~ 127 bytes), vdd33_const must be set to the real power supply voltage of Pin 3 and Pin 4. RF Initialization Parameter The working power voltage range of ESP8285 is between 1.8V and 3.6V, while the unit of vdd33_const is 0.1V, therefore, the effective value range of vdd33_const is 18 to 36. RF Calibration Process Optimize the RF circuit conditions based on the value of vdd33_const. The permissible error is ±0.2V.
5. Electrical Specifications $ 5. Electrical Specifications 5.1. Electrical Characteristics Table 5-1. Electrical Characteristics Parameters Conditions Min Typical Max Unit Storage Temperature Range - -40 Normal 125 ℃ Maximum Soldering Temperature IPC/JEDEC JSTD-020 - - 260 ℃ Working Voltage Value - 2.5 3.3 3.6 V VIL/VIH - -0.3/0.75VIO - 0.25VIO/3.6 VOL/VOH - N/0.8VIO - 0.
5. Electrical Specifications $ 📖 Notes: ① Modem-sleep mode is used in the applications that require the CPU to be working, as in PWM or I2S applications. According to 802.11 standards (like U-APSD), it shuts down the Wi-Fi Modem circuit while maintaining a Wi-Fi connection with no data transmission to optimize power consumption. E.g. in DTIM3, maintaining a sleep of 300 ms with a wake-up of 3 ms cycle to receive AP’s Beacon packages at interval requires about 15 mA of current.
6. Package Information $ 6. Package Information ! Figure 6-1. ESP8285 Package Espressif $ /$ 25 21 2017.
Appendix A $ A. Appendix—Pin List For detailed pin information, refer to ESP8266 Pin List. • Digital Die Pin List • Buffer Sheet • Register List • Strapping List 📖 Notes: • INST_NAME refers to the IO_MUX REGISTER defined in eagle_soc.h, for example MTDI_U refers to PERIPHS_IO_MUX_MTDI_U. • Net Name refers to the pin name in schematic. • Function refers to the multifunction of each pin pad. • Function number 1 ~ 5 correspond to FUNCTION 0 ~ 4 in SDK. For example, set MTDI to GPIO12 as follows.
Appendix B $ B. Appendix—Learning Resources B.1. Must-Read Documents • ESP8266EX Datasheet Description: This document introduces the specifications of ESP8266EX, including an overview of the features, protocols, technical parameters and applications. It also introduces pin layout and the relevant description, as well as major functional modules and protocols applied on ESP8266EX (CPU, flash and memory, clock, radio, Wi-Fi, and low-power management).
Appendix B $ • ESP8266 RTOS SDK API Reference Description: This document lists ESP8266_RTOS_SDK APIs, including functions for WiFi related APIs and boot APIs, etc. • FAQ B.2. Must-Have Resources • ESP8266 SDKs Description: This website page provides links to the latest version of ESP8266 SDK and the older ones. • ESP8266 Tools Description: This website page provides links to the ESP8266 flash download tools and ESP8266 performance evaluation tools.
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