Datasheet

15:13
/
/
/
12:0
R/W
0x0100
The DRC gain curve offset O parameter setting(the O = [reg
af[12:0], reg b0] is 5.24 format 2s complement )
Reg b0h_DAC DAP Low Gain Offset Parameter Register
Default: 0x0000
Register Name: AC_DAC_DAPLGOPA
Bit
Read/Write
Default
Description
15:0
R/W
0x0000
The DRC gain curve offset O parameter setting(the K = [reg
af[12:0], regb0] is 5.24 format 2s complement )
Reg b1h _DAC DAP Optimum Register
Default: 0x0000
Register Name: AC_DAC_DAPOPT
Bit
Read/Write
Default
Description
15:6
/
/
/
5
R/W
0
DRC gain default value setting
0: The default gain is 1
1: The default gain is 0
4:0
R/W
0x00
The hysteresis of the gain smooth filter to use the decay time
coefficient or the attack time coefficient.
When in the decay time state, if g(n-1)-g(n)>hysteresis, then
the state will change to attack time state, and when in the
attack time, if g(n)-g(n-1)>hysteresis, then the state will
change to decay time state. Note the hysteresis of 0x00 and
0x04 is the same.
00000:
16
2

00001:
19
2

00010:
18
2

00011:
17
2

00100:
16
2

-----------------
10011:
1
2

10100 ~11111: 1
hysteresis =
20
2
n
,except n=0x00, and n less 0x14.
Reg b5h_DAC DAP Enable Register
Default: 0x0000
Register Name: DAC_DAP_ENA
Bit
Read/Write
Default
Description
15
R/W
0x0
I2S1_DAC0_DRC_ENA
I2S1 DAC timeslot 0 DRC enable
0: Disable
1: Enable
14
R/W
0x0
Reserved
13
R/W
0x0
I2S1_DAC1_DRC_ENA
I2S1 DAC timeslot 1 DRC enable