Datasheet

10: (I2S1_DACL1+I2S1_DACR1)
11: (I2S1_DACL1+I2S1_DACR1)/2
5:4
R/W
0x0
I2S1_DACR1_SRC
I2S1 DAC Timeslot 1 right channel data source select
00: I2S1 DACR1
01: I2S1 DACL1
10: (I2S1 DACL1+I2S1 DACR1)
11: (I2S1 DACL1+I2S1 DACR1)/2
3
R/W
0x0
I2S1_DACP_ENA
I2S1 DAC Companding enable(8-bit mode only)
00: Disable
01: Enable
2
R/W
0x0
I2S1_ DACP_SEL
I2S1 DAC Companding mode select
0: A-law
1: u-law
1
R/W
0x0
Reserved
0
R/W
0x0
I2S1_LOOP_ENA
I2S1 loopback enable
0: No loopback
1: Loopback(SDOUT1 data output to SDOUT1 data input)
Reg 13h_I2S1 Digital Mixer Source Select Register
Default: 0x0000
Register Name: I2S1_MXR_SRC
Bit
Read/Write
Default
Description
15:12
R/W
0x0
I2S1_ADCL0_MXL_SRC
I2S1 ADC Timeslot 0 left channel mixer source select
0: Disable 1: Enable
Bit15: I2S1_DA0L data
Bit14: Reserved
Bit13: ADCL data
Bit12: Reserved
11:8
R/W
0x0
I2S1_ADCR0_MXR_SRC
I2S1 ADC Timeslot 0 right channel mixer source select
0: Disable 1: Enable
Bit11: I2S1_DA0R data
Bit10: Reserved
Bit9: ADCR data
Bit8: Reserved
7:6
R/W
0x0
I2S1_ADCL1_MXR_SRC
I2S1 ADC Timeslot 1 left channel mixer source select
0: Disable 1: Enable
Bit7: Reserved
Bit6: ADCL data
5:4
R/W
0x0
Reserved
3:2
R/W
0x0
I2S1_ADCR1_MXR_SRC