Datasheet

9:8
R/W
0x0
I2S1CLK_SRC
I2S1CLK Source Select
00: MLCK1
01: Reserved
1X: PLL
7:4
R/W
0x0
Reserved
3
R/W
0x0
SYSCLK_ENA
SYSCLK Enable
0: Disable
1: Enable
2:0
R/W
0x0
Reserved
Reg 04h_Module Clock Enable Control Register
Default: 0x0000
Register Name: MOD_CLK_ENA
Bit
Read/Write
Default
Description
15:0
R/W
0x0
Module clock enable control
0-Clock disable
1-Clock enable
BIT15-I2S1
BIT14-Reserved
BIT13-Reserved
BIT12-Reserved
BIT11-Reserved
BIT10-Reserved
BIT9-Reserved
BIT8-Reserved
BIT7-HPF & AGC
BIT6-HPF & DRC
BIT5-Reserved
BIT4-Reserved
BIT3-ADC Digital
BIT2-DAC Digital
BIT1-Reserved
BIT0-Reserved
Reg 05h_Module Reset Control Register
Default: 0x0000
Register Name: MOD_RST_CTRL
Bit
Read/Write
Default
Description
15:0
R/W
0x0
Module reset control
0-Reset asserted
1-Reset de-asserted
BIT15-I2S1
BIT14-Reserved
BIT13-Reserved
BIT12-Reserved
BIT11-Reserved