Datasheet

Reg 02h_PLL Configure Control 2 Register
Default: 0x0000
Register Name: PLL_CTRL2
Bit
Read/Write
Default
Description
15
R/W
0x0
PLL_EN
PLL Enable
0: Disable
1: Enable
The PLL output FOUT= FIN*N/(M*(2K+1)), N=N_i+N_f;
14
R
0x0
PLL Locked status
0: Not locked or not enabled
1: Enabled and locked
13:4
R/W
0x0
PLL_PREDIV_NI
PLL Integer Part of Pre-Divider Factor N.
Factor=0，N_i=0 ;
Factor=1，N_i=1 ;
...
Factor=1023, N_i=1023 ;
3
/
/
/
2:0
R/W
0x0
PLL_POSTDIV_NF
PLL Fractional Part of Pre-Divider Factor N.
Factor=0，N_f=0*0.2 ;
Factor=1，N_f=1*0.2 ;
...
Factor=7, N_f=7*0.2 ;
Reg 03h_System Clocking Control Register
Default: 0x0000
Register Name: SYSCLK_CTRL
Bit
Read/Write
Default
Description
15
R/W
0x0
PLLCLK_ENA
PLLCLK Enable
0: Disable
1: Enable
14
R/W
0x0
Reserved
13:12
R/W
0x0
PLLCLK_SRC
PLL Clock Source Select
00: MCLK1
01: Reserved
10: BCLK1
11: Reserved
11
R/W
0x0
I2S1CLK_ENA
I2S1CLK Enable
0: Disable
1: Enable
10
R/W
0x0
Reserved