Datasheet

11.4. TWI/RSB Interface
AC101 can support two series control interface protocol for writing to or read back from registers on SCK
and SDA pins . One is TWI interface, the other is RSB interface. RSB is top-priority for higher efficiency
and lower power consumption.
11.4.1. TWI Interface
TWI is a 2-wire (SCK/SDA) half-duplex serial communication interface, supporting only slave mode. SCK
is used for clock and SDA is for data. SCK clock supports up to 400 KHz rate and SDA data is a open drain
structure.
A master controller initiates the transmission by sending a “start” signal, which is defined as a high-to-low
transition at SDA while SCK is high. The first byte transferred is the slave address. It is a 7-bit chip address
followed by a R/W bit. The chip address must be 0011010x. The R/W bit indicates the slave data transfer
direction. Once an acknowledge bit is received, the data transfer starts to proceed on a byte-by-byte basis in
the direction specified by the R/W bit. The master can terminate the communication by generating a “stop”
signal, which is defined as a low-to-high transition at SDA while SCK is high.
Figure 7 TWI Interface
The formats of “write” and “read” instructions are shown in below.
Figure 8 TWI Read and Write