Datasheet

11.3. PLL
A Phase-Locked Loop(PLL) is used to provide a flexible input clock range from 128KHz to 24MHz. The
source of the PLL can be set to MCLK1 or BCLK1 by setting register. The PLL output is always used to
provide the system clock(SYSCLK) of AUDIO codec when 24.576MHz or 22.5792MHz can not be
provided from MCLK.
The PLL transmit formula as below:
FOUT =(FIN * N) / (M * (2K+1)) ; （N= N_i + 0.2*N_f）
Table 1 clock setting for SYSCLK=24.576 MHz
FIN
M
N
K
FOUT
128K
1
576
1
24.576M
192K
1
384
1
24.576M
256K
1
288
1
24.576M
384K
1
192
1
24.576M
...
....
...
1
24.576M
6M
25
307.2
1
24.576M
13M
42
238.2
1
24.576M
19.2M
25
96
1
24.576M
Table 2 clock setting for SYSCLK=22.5792 MHz
FIN
M
N
K
FOUT
128K
1
529.2
1
22.5792M
192K
1
352.8
1
22.5792M
256K
1
264.6
1
22.5792M
384K
1
176.4
1
22.5792M
...
....
...
1
22.5792M
6M
38
429
1
22.5789M
13M
19
99
1
22.5789M
19.2M
25
88.2
1
22.5792M