Datasheet

11.2. Clock
The system clock(SYSCLK) of AC101 must be 512*fs(fs=48KHz or 44.1KHz). So the system should
arrange the divider to generate 24.576MHz for audio clock series of 48KHz or 22.5792MHz for series of
44.1KHz.
SYSCLK is the reference of ADC, DAC, DVC, MIXER, AGC and DRC module. SYSCLK can be selected
from I2S1CLK which derived from MCLK1 or PLL. MCLK1 are always provided externally while the
PLL reference clock can be select from MCLK1 and BCLK1.
I2S1CLK is the reference of the first I2S clocking zone. In master mode, LRCK and BCLK are derived
internally from I2SnCLK. In slave mode, LRCK and SCLK are supplied externally and BCLK can be used
as the PLL input reference.
There are also an internal Oscillator to generate a clock signal for direct-path mode. In this mode, the
oscillator supply clock to charge pump, adjustment circuit, headphone detect circuite.g... In direct-path case,
no external clock need .
Figure 6 Clocking Management