AC101 User Manual Revision 1.1 2015/1/11 Copyright©2014 X-Powers Technology. All Rights Reserved.
Declaration This documentation is the original work and copyrighted property of X-Powers. Reproduction in whole or in part must obtain the written approval of X-Powers and give clear acknowledgement to the copyright owner. The information furnished by X-Powers is believed to be accurate and reliable. X-Powers reserves the right to make changes in circuit design and/or specifications at any time without notice. X-Powers does not assume any responsibility and liability for its use.
About Documentation This documentation of AC101 is intended to be used by board-level product designers and product software developers. The manual assumes that the reader has a background in computer engineering and/or software engineering and understands concepts of digital system design, microprocessor architecture, Input / Output (I/O) devices, industry standard communication and device interface protocols.
Revision History Version Date Description V1.0 2014/12/1 Completed Draft V1.
Table of Contents Declaration......................................................................................................................................................... 2 About Documentation........................................................................................................................................3 Revision History................................................................................................................................................
11.4.1. TWI Interface.......................................................................................................................25 11.4.2. RSB Interface.......................................................................................................................26 11.5. I2S/PCM Interface.......................................................................................................................... 28 11.6. Stereo ADC.............................................................
Reg 04h_Module Clock Enable Control Register...................................................................................47 Reg 05h_Module Reset Control Register................................................................................................47 Reg 06h_ADDA Sample Rate Configuration Register........................................................................... 48 Reg 10h_I2S1 BCLK/LRCK Control Register.................................................................................
Reg 55h_Output Mixer Source Boost Register....................................................................................... 64 Reg 56h_Headphone Output Control Register........................................................................................64 Reg 58h_Speaker Output Control Register............................................................................................. 65 Reg a0h_DAC DAP Control Register...............................................................................
1. Description The AC101 is a highly integrated audio codec designed for player and tablet application platforms. It has one I2S/PCM interface, 2 channel DAC and 2 channel ADC with a high level of mixed-signal integration. An integrated digital PLL supports a large range of input/output frequencies, and It can generate required audio clocks for codec from standard audio crystal rate such as 22.5792MHz and 24.576MHz, also can be from common reference clock frequencies such as 12MHz, 13MHz and 19.
2. Features The AC101 features: • 2 ADCs and 2 DACs @ 24-bit and inter PLL processing with flexible clocking scheme • Up to 100dB SNR during DAC playback path (A ' weight) • Up to 95dB SNR during ADC record path (A ' weight) • Capless stereo headphone driver – Integrated charge pump for 0V reference – 18mW @1.
3. Applications • Tablets • Box/Player 4. Functional Block Diagram 4.1.
4.2.
5.
6.
7. Pin/Signal Description This chapter describes the 68 pins of AC101 from four aspects: pin number, signal name, type, and pin definition. All the pins are classified into four groups, including digital IO pin, analog IO pin, filter/reference, and power/ground. There are five pin types here: O for output, I for input, I/O for input/output, P for power, and G for ground.
8 AVCC P Analog power 7 AGND G Analog ground 22 CPVDD P Analog power for headphone charge pump 20 CPVEE P Charge pump negative decoupling Pin 15 VPP P Headphone PA positive voltage input 16 VEE P Headphone PA negative voltage input 35 VDD_CORE P Digital power for digital core 33 VCC_IO1 P Digital power for digital I/O buffer（I2S1） 25 VCC_IO0 P Digital power for digital I/O buffer（I2C and RSB） 36 LDOIN P Input power for Audio_LDO 34 BYPASS P Bypass for Digital core
8. Electrical Characteristics 8.1. Absolute Maximum Ratings Absolute maximum ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under electrical characteristics at the test conditions specified. Symbol Parameter MIN MAX Unit LDO_IN LDO Input power for Audio CODEC -0.3 3.
8.3. Static Characteristics Symbol Parameter Test condition Min Typical Max VIN Input Voltage Range -- -0.3 -- VIH High Level Input Voltage VCCIO=3.0v 2.4 -- 3.6 VCCIO=1.8V 1.4 -- 1.98 VIL Low Level Input Voltage VCCIO=3.0v -0.3 -- 0.7 VCCIO=1.8V -0.3 -- 0.7 VOH High Level Input Voltage VCCIO=3.0v 2.7 -- NA VCCIO=1.8V 1.5 -- NA VOL Low Level Input Voltage VCCIO=3.0v NA -- 0.4 VCCIO=1.8V NA -- 0.
9. Analog Performance Characteristics PARAMETER DAC Output Path Performance TEST CONDITIONS MIN TYP MAX UINT DAC to Headphone on HPOUTL or HPOUTR(R=10kΩ) FScale Output Level 0dB 1KHz 0.9 Vrms SNR(A-weighted) 0dB 1KHz 100 dB THD+N(NO-Aweight) 0dB 1KHz -84 dB Crosstalk（L/R） 0dB 1KHz -88/-88 dB DAC to Headphone on HPOUTL or HPOUTR(R=16Ω) FScale Output Level 0dB 1KHz 0.
Crosstalk（L/R） Bypass Path Performance 1KHz -85/-85 dB FScale Input Level 0dB Gain 1KHz 0.
10. Typical Power Consumption Default Test Conditions: LDOIN=CPVDD=1.5V,AVCC=3.0V,VCC-IO1=1.8V,VCC-IO0=3.0V OPERATING TEST CONDITIONS LDOIN AVCC VCC-IO1 VCC-IO0 CPVDD LDO enabled LDOIN,VCC-IO0 supplies, 1.8V 3V 1.8V 3V 1.8V XTAL enabled 32.768KHz clock, 0uA 0uA 0uA 12uA 0uA All supplies present, 1.8V 3V 1.8V 3V 1.8V 73uA 62uA 0uA 12uA 0uA 1.8V 3V 1.8V 3V 1.8V 24bit I2S,Slave mode 1.5mA 4.1mA 0.013mA 12uA 2.4mA fs=44.1KHz, 1.8V 3V 1.8V 3V 1.8V 1.4mA 4.5mA 0.
11. Function Description 11.1. Power There are a Power-Reset circuit in AC101 used to reset all the circuit and register to a standby state after power up. The Power-Reset circuit make all the supply power need no specific timing. All the supply voltages are illustrated in the below figure. Figure 5 Power Management VDD-CORE is 1.2V for audio digital core power generated from LODIN pin, which also can be direct supplied from VDD-CORE pin. VDD-IO0 is digital I/O power for I2C/RSB .
11.2. Clock The system clock(SYSCLK) of AC101 must be 512*fs(fs=48KHz or 44.1KHz). So the system should arrange the divider to generate 24.576MHz for audio clock series of 48KHz or 22.5792MHz for series of 44.1KHz. SYSCLK is the reference of ADC, DAC, DVC, MIXER, AGC and DRC module. SYSCLK can be selected from I2S1CLK which derived from MCLK1 or PLL. MCLK1 are always provided externally while the PLL reference clock can be select from MCLK1 and BCLK1.
11.3. PLL A Phase-Locked Loop(PLL) is used to provide a flexible input clock range from 128KHz to 24MHz. The source of the PLL can be set to MCLK1 or BCLK1 by setting register. The PLL output is always used to provide the system clock(SYSCLK) of AUDIO codec when 24.576MHz or 22.5792MHz can not be provided from MCLK. The PLL transmit formula as below: FOUT =(FIN * N) / (M * (2K+1)) ; Table 1 FIN M 128K （N= N_i + 0.2*N_f） clock setting for SYSCLK=24.576 MHz N K FOUT 1 576 1 24.
11.4. TWI/RSB Interface AC101 can support two series control interface protocol for writing to or read back from registers on SCK and SDA pins . One is TWI interface, the other is RSB interface. RSB is top-priority for higher efficiency and lower power consumption. 11.4.1. TWI Interface TWI is a 2-wire (SCK/SDA) half-duplex serial communication interface, supporting only slave mode. SCK is used for clock and SDA is for data. SCK clock supports up to 400 KHz rate and SDA data is a open drain structure.
11.4.2. RSB Interface RSB interface supports a special protocols with a simplified two wire protocol on a push-pull bus. So the transfer speed can be up to 10MHz and the performance will be improved much. AC101 works only in slave mode. RSB support multi-slaves. It uses CK as clock and uses CD to transmit command and data.the Bus Topology is showed below: Figure 9 RSB Bus Topology The start bit marks the beginning of a transaction with the slave device.
Figure 12 RTSADDR command Read command is used to read data from device.It has byte,half word and word operation.When devices receives the command,they shall check if the command's RTSADDR matches their own RTSADDR.The device's RTSADDR is set by set run-time slave address(RTSADDR) command. Figure 13 Read command Write command is used to write data to the devices.It has byte,half word and word operation.When devices receive the command,they shall check if the command's RTSADDR matches their own RTSADDR.
11.5. I2S/PCM Interface There are one I2S/PCM interface which can be configured as master mode or slave mode in AC101. In the general case, the digital audio interface uses four pins as below: BCLK: Bit clock for data synchronization LRCK: Left/Right data alignment clock SDOUT: output data for ADC data SDIN: input data for DAC data I2S audio interface support four different data formats as below.
Figure 16 Figure 17 Left Justified mode Right Justified mode Figure 18 Pcm mode A(LRCK_INV=0) Figure 19 Pcm mode B(LRCK_INV=1)
Figure 20 Pcm mode A mono(LRCK_INV=0) Figure 21 Pcm mode B mono(LRCK_INV=1) Figure 22 I2S TDM mode
Figure 23 PCM TDM mode
11.6. Stereo ADC The stereo ADC is used for recording stereo sound. The sample rate of the stereo ADC can not be independent of DAC sample rate. In other words, the stereo ADC and DAC must work at a same sample rate. The sample rate is configured by the register ADDA_FS_I2S1. In order to save power, the left and right analog ADC part can be enabled/disabled separately by setting register ADC_APC_CTRL Bit15 & Bit11. The digital ADC part can be enabled/disabled by ADC_DIG_CTRL Bit15.
11.8.3. Digital Mixers The digital mixers are provided for digital audio data mixing on one I2S path, two ADC output paths and two input paths to the stereo DAC. It's separately controlled by the register I2S1_MXR_SRC and DAC_MXR_SRC.
11.9. Analogue Audio Input Path The codec supports five Analogue Audio Input paths: LINEINL/R MIC1P/N,MIC2P/N 11.9.1. Microphone Input MICIN1P/N, MICIN2P/N provide differential input that can be mixed into the ADC record mixer, or DAC output mixer. MICIN is high impedance, low capacitance input suitable for connection to a wide range of differential microphones of different dynamics and sensitive. There are two microphone pre-amplifiers for the 2 differential microphone inputs.
11.10. Analogue Audio Output Path The codec supports five Analogue Audio Output paths: HPOUTL/R, HPOUTFB SPOLP/N SPORP/N 11.10.1. Headphone Output HPOUTL/R provides two-channel single-ended output to headphone driver. The HPOUTL/R PA input source can be selected from output mixer or directly from DAC by register HPOUT_CTRL Bit15 & Bit14 set. It also can be muted by register HPOUT_CTRL Bit13 & Bit12 set. The headphone PA power up or down by register HPOUT_CTRL Bit11 set.
SPORP/N input source is selected from (left+right) output mixer avoiding sound loss. The volume control is logarithmic with an 43.5dB rang in 1.5dB step from -43.5dB to 0dB. The left and right speaker output buffer can independently power up or down by register SPKOUT_CTRL Bit11 & Bit7 set.
11.11. Digital Microphone Interface AC101 supports a stereo digital microphone interface. The DMICCLK/ DMICDAT pins are multiplexed on the MIC3P/MIC3N pins. The circuit share decimation filter with audio ADC. And DMICCLK can be output 128fs (fs= ADC sample rate). Digital Microphone power usually falls between the range 1.6V-3.6V, typical 1.8V. frequency is between the the range 1.0MHz-3.25MHz, typical 2.4MHz.
11.12. Audio Jack Detect The microphone bias output pin HBIAS provide a low noise reference voltage suitable for biasing electrets type microphones and the associated external resistor biasing network. Hbias is designed to drive headset microphone, and a bias current detect function is provided for external accessory detection by measuring the Hbias current. In some application, it's used to detect the insertion/removal of a audio jack and the button press.
11.13. Interrupt The Interrupt circuits in AC101 generate an Interrupt (IRQ) event to enable the detection of audio jack status. The Interrupt pin IRQ_AUDIO is open-drain. It's usually drives a high level voltage via the external pull-up resistor while it output a low level when the IRQ is active.
11.14. Digital Audio Process for DAC The DAP System Block Diagram For DAC.
11.14.1. High Pass Filter The DAP has individual channel high pass filter that can be enabled and disabled. The filter cutoff frequency is less than 1Hz. H ( z) 1 z 1 1 az 1 11.14.2. Dynamic Range Control The dynamic range control(DRC) can be enabled in the digital playback path of AC101. It automatically adjusts the wide volume gain to flatten volume level.
Energy Filter The Energy Filter is to estimate of the RMS value of the audio data stream into DRC, and has two parameters, which determine the time window over which RMS to be made. The parameter is computed by 1 e 2.
The O is the offset of the compression static curve. The offset input to the coefficient register is computed by Oin 10 O / 20 There, O is -24dB to 24dB. For example, it desired to set O=6dB, then Oin 10 6/ 20 1.995 , and the 5.24 format of the Oin is 0x1FE_C982. Gain Smooth Filter The Gain Smooth Filter is to smooth the gain and control the ratio of gain increase and decrease. The decay time and attack is shown in Figure 5.
12.
Reg 00h_Chip Soft Reset Register Default: 0x0101 Register Name: CHIP_AUDIO_RST Bit Read/Write Default Description 15:0 R/W 0x0101 Writing to this register resets all register to their default state. Reading from this register will indicate device type and version.
Reg 02h_PLL Configure Control 2 Register Default: 0x0000 Bit 15 14 Read/Write R/W R Register Name: PLL_CTRL2 Default Description 0x0 PLL_EN PLL Enable 0: Disable 1: Enable The PLL output FOUT= FIN*N/(M*(2K+1)), N=N_i+N_f; 0x0 PLL Locked status 0: Not locked or not enabled 1: Enabled and locked 13:4 R/W 0x0 PLL_PREDIV_NI PLL Integer Part of Pre-Divider Factor N. Factor=0，N_i=0 ; Factor=1，N_i=1 ; ...
9:8 R/W 0x0 I2S1CLK_SRC I2S1CLK Source Select 00: MLCK1 01: Reserved 1X: PLL 7:4 R/W 0x0 Reserved 3 R/W 0x0 SYSCLK_ENA SYSCLK Enable 0: Disable 1: Enable 2:0 R/W 0x0 Reserved Reg 04h_Module Clock Enable Control Register Default: 0x0000 Bit 15:0 Read/Write R/W Register Name: MOD_CLK_ENA Default Description 0x0 Module clock enable control 0-Clock disable 1-Clock enable BIT15-I2S1 BIT14-Reserved BIT13-Reserved BIT12-Reserved BIT11-Reserved BIT10-Reserved BIT9-Reserved BIT8-Reserved BIT7-
BIT10-Reserved BIT9-Reserved BIT8-Reserved BIT7-HPF & AGC BIT6-HPF & DRC BIT5-Reserved BIT4-Reserved BIT3-ADC Digital BIT2-DAC Digital BIT1-Reserved BIT0-Reserved Reg 06h_ADDA Sample Rate Configuration Register Default: 0x0000 Bit Read/Write Register Name: I2S_SR_CTRL Default Description 15:12 R/W 0x0 ADDA_FS_I2S1 ADDA Sample Rate synchronised with I2S1 clock zone 0000: 8KHz 0001: 11.025KHz 0010: 12KHz 0011: 16KHz 0100: 22.05KHz 0101: 24KHz 0110: 32KHz 0111: 44.
12:9 8:6 5:4 3:2 1 0 R/W R/W R/W R/W R/W R/W 0x0 I2S1_BCLK_DIV Select the I2S1CLK/BCLK1 ratio 0000: I2S1CLK/1 0001: I2S1CLK/2 0010: I2S1CLK/4 0011: I2S1CLK/6 0100: I2S1CLK/8 0101: I2S1CLK/12 0110: I2S1CLK/16 0111: I2S1CLK/24 1000: I2S1CLK/32 1001: I2S1CLK/48 1010: I2S1CLK/64 1011: I2S1CLK/96 1100: I2S1CLK/128 1101: I2S1CLK/192 1110: Reserved 1111: Reserved 0x0 I2S1_LRCK_DIV Select the BCLK1/LRCK ratio 000: 16 001: 32 010: 64 011: 128 100: 256 1xx: Reserved 0x0 I2S1_WORD_SIZ I2S1 digital int
Reg 11h_I2S1 SDOUT Control Register Default: 0x0000 Bit 15 14 13 12 11:10 9:8 7:6 5:4 3 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W Register Name: I2S1_SDOUT_CTRL Default Description 0x0 I2S1_ADCL0_ENA I2S1 ADC Timeslot 0 left channel enable 0: Disable 1: Enable 0x0 I2S1_ADCR0_ENA I2S1 ADC Timeslot 0 right channel enable 0: Disable 1: Enable 0x0 I2S1_ADCL1_ENA I2S1 ADC Timeslot 1 left channel enable 0: Disable 1: Enable 0x0 I2S1_ADCR1_ENA I2S1 ADC Timeslot 1 right channel ena
1: Enable 2 1:0 R/W R/W 0x0 I2S1_ ADCP_SEL I2S1ADC Companding mode select 0: A-law 1: u-law 0x0 I2S1_SLOT_SIZ Select the slot size(only in TDM mode) 00: 8 01: 16 10: 32 11: Reserved Reg 12h_I2S1 SDIN Control Register Default: 0x0000 Bit 15 14 13 12 11:10 9:8 7:6 Read/Write R/W R/W R/W R/W R/W R/W R/W Register Name: I2S1_SDIN_CTRL Default Description 0x0 I2S1_DACL0_ENA I2S1 DAC Timeslot 0 left channel enable 0: Disable 1: Enable 0x0 I2S1_DACR0_ENA I2S1 DAC Timeslot 0 right chann
10: (I2S1_DACL1+I2S1_DACR1) 11: (I2S1_DACL1+I2S1_DACR1)/2 5:4 3 R/W R/W 0x0 I2S1_DACR1_SRC I2S1 DAC Timeslot 1 right channel data source select 00: I2S1 DACR1 01: I2S1 DACL1 10: (I2S1 DACL1+I2S1 DACR1) 11: (I2S1 DACL1+I2S1 DACR1)/2 0x0 I2S1_DACP_ENA I2S1 DAC Companding enable(8-bit mode only) 00: Disable 01: Enable 2 R/W 0x0 I2S1_ DACP_SEL I2S1 DAC Companding mode select 0: A-law 1: u-law 1 R/W 0x0 Reserved 0x0 I2S1_LOOP_ENA I2S1 loopback enable 0: No loopback 1: Loopback(SDOUT1 data outpu
I2S1 ADC Timeslot 1 right channel mixer source select 0: Disable 1: Enable Bit3: Reserved Bit2: ADCR data 1:0 R/W 0x0 Reserved Reg 14h_I2S1 Volume Control 1 Register Default: 0xA0A0 Bit 15:8 7:0 Read/Write R/W R/W Register Name: I2S1_VOL_CTRL1 Default Description 0xA0 I2S1_ADCL0_VOL I2S1 ADC Timeslot 0 left channel volume (-119.25dB To 71.25dB, 0.75dB/Step) 0x00: Mute 0x01: -119.25dB ……………… 0x9F = -0.75dB 0xA0 = 0dB 0xA1 = 0.75dB ……………… 0xFF = 71.
7:0 R/W 0xA0 I2S1_ADCR1_VOL I2S1 ADC Timeslot 1 right channel volume (-119.25dB To 71.25dB, 0.75dB/Step) 0x00: Mute 0x01: -119.25dB ……………… 0x9F = -0.75dB 0xA0 = 0dB 0xA1 = 0.75dB ……………… 0xFF = 71.25dB Reg 16h_I2S1 Volume Control 3 Register Default: 0xA0A0 Bit 15:8 7:0 Read/Write R/W R/W Register Name: I2S1_VOL_CTRL3 Default Description 0xA0 I2S1_DACL0_VOL I2S1 DAC Timeslot 0 left channel volume (-119.25dB To 71.25dB, 0.75dB/Step) 0x00: Mute 0x01: -119.25dB ……………… 0x9F = -0.
……………… 0x9F = -0.75dB 0xA0 = 0dB 0xA1 = 0.75dB ……………… 0xFF = 71.25dB 7:0 R/W 0xA0 I2S1_DACR1_VOL I2S1 DAC Timeslot 1 right channel volume (-119.25dB To 71.25dB, 0.75dB/Step) 0x00: Mute 0x01: -119.25dB ……………… 0x9F = -0.75dB 0xA0 = 0dB 0xA1 = 0.75dB ……………… 0xFF = 71.
Reg 40h_ADC Digital Control Register Default: 0x0000 Bit 15 14 Read/Write R/W R/W Register Name: ADC_DIG_CTRL Default Description 0x0 ENAD ADC Digital part enable 0: Disable 1: Enable 0x0 ENDM Digital microphone enable 0: Analog ADC mode 1: Digital microphone mode 13 R/W 0x0 ADFIR32 Enable 32-tap FIR filter 0: 64-tap 1: 32-tap 12:4 R/W 0x0 Reserved 0x0 ADOUT_DTS ADC Delay Time For transmitting data after ENAD 00:5ms 01:10ms 10:20ms 11:30ms 3:2 R/W 1 R/W 0x0 ADOUT_DLY ADC Delay Fun
(-119.25dB To 71.25dB, 0.75dB/Step) 0x00: Mute 0x01: -119.25dB ……………… 0x9F = -0.75dB 0xA0 = 0dB 0xA1 = 0.75dB ……………… 0xFF = 71.
Bit 15:14 Read/Write R/W Default Description 0x0 HMIC_SAMPLE_SELECT Down Sample Setting Select 00: Down by 1, 128Hz 01: Down by 2, 64Hz 10: Down by 4, 32Hz 11: Down by 8, 16Hz 13 R/W 0x0 HMIC_TH2_HYSTERESIS Hmic Hysteresis Threshold2 0: no Hysteresis 1: Key Up when Data <= (Hmic_th2-1) 12:8 R/W 0x0 HMIC_TH2 Hmic_th2 for detecting Key down or Key up.
0: No Pending Interrupt 1: Key down Irq Pending Interrupt 0 R/W 0x0 HMIC_DATA_PENDING Hmic Data Irq pending bit, write 1 to clear 0: No Pending Interrupt 1: Data Irq Pending Interrupt Reg 48h_DAC Digital Control Register Default: 0x0000 Bit 15 14 Read/Write R/W R/W Register Name: DAC_DIG_CTRL Default Description 0x0 ENDA.
(-119.25dB To 71.25dB, 0.75dB/Step) 0x00: Mute 0x01: -119.25dB ……………… 0x9F = -0.75dB 0xA0 = 0dB 0xA1 = 0.75dB ……………… 0xFF = 71.
7:0 R/W 0x0 Reserved Reg 50h_ADC Analog Control Register Default:0x3340 Bit 15 14:12 R/W R/W R/W Register Name: ADC_APC_CTRL Default Description 0x0 ADCREN ADC Right channel Enable 0: Disable; 1: Enable 0x3 ADCRG ADC Right channel input Gain control From -4.5dB to 6dB, 1.5dB/step, default is 0dB 11 R/W 0x0 ADCLEN ADC Left channel Enable 0: Disable; 1: Enable 10:8 R/W 0x3 ADCLG ADC Left channel input Gain control From -4.5dB to 6dB, 1.
13:7 6:0 R/W R/W 0x0 RADC_MIXMUTE Right ADC Mixer Mute Control: 0: Mute; 1:On Bit 13: MIC1 Boost stage Bit 12: MIC2 Boost stage Bit 11: LINEINL-LINEINR Bit 10: LINEINR Bit 9: Reserved Bit 8: Right output mixer Bit 7: Left output mixer 0x0 LADC_MIXMUTE Left ADC Mixer Mute Control: 0: Mute; 1:On Bit 6: MIC1 Boost stage Bit 5: MIC2 Boost stage Bit 4: LINEINL-LINEINR Bit 3: LINEINL Bit 2: Reserved Bit 1: Left output mixer Bit 0: Right output mixer Reg 52h_ADC Source Boost Control Register Default:0x4444
Reg 53h_Output Mixer & DAC Analog Control Register Default:0x0f80 Bit 15 14 13 12 R/W R/W R/W R/W R/W Register Name: OMIXER_DACA_CTRL Default Description 0x0 DACAREN Internal DAC Analog Right channel Enable 0:Disable 1:Enable 0x0 DACALEN Internal DAC Analog Left channel Enable 0:Disable 1:Enable 0x0 RMIXEN Right Analog Output Mixer Enable 0:Disable 1:Enable 0x0 LMIXEN Left Analog Output Mixer Enable 0:Disable 1:Enable 11:9 R/W 0xf HP_DCRM_EN Headphone DC offset remove function enable
Bit 6: MIC1 Boost stage Bit 5: MIC2 Boost stage Bit 4: LINEINL-LINEINR Bit 3: LINEINL Bit 2: Reserved Bit 1: DACL Bit 0: DACR Reg 55h_Output Mixer Source Boost Register Default:0x56DB Bit 15:14 R/W R/W Register Name: OMIXER_BST1_CTRL Default Description 0x1 HBIASSEL HMICBIAS voltage level select 00: 1.88V 01: 2.09V 10: 2.33V 11: 2.50V 13:12 R/W 0x1 MBIASSEL MMICBIAS voltage level select 00: 1.88V 01: 2.09V 10: 2.33V 11: 2.
13 R/W 0x0 RHPPA_MUTE All input source to Right Headphone PA mute, including Right Output mixer and Internal DACR: 0:Mute, 1: On 12 R/W 0x0 LHPPA_MUTE All input source to Left Headphone PA mute, including Left Output mixer and Internal DACL: 0:Mute, 1: On 11 R/W 0x0 10 / / 9:4 R/W 3:2 1:0 R/W R/W 0x0 HPPA_EN Right & Left Headphone Power Amplifier Enable 0: Disable 1: Enable / HP_VOL Headphone Volume Control, (HPVOL): Total 64 level, from 0dB to -62dB, 1dB/step, mute when 000000 0x0 HP
Left speaker negative output enable 0: Disable; 1: Enable 6 / 5 R/W 4:0 R/W / / 0x0 LSPK_EN Left Speaker Enable 0: Disable; 1: Enable 0x0 SPK_VOL Right & Left speaker VOLume control Total 31 level, from 0dB to -43.5dB, 1.
Reg a4h_DAC DAP Left Low Energy Average Coef Register Default: 0x0000 Bit 15:0 Read/Write R/W Register Name: AC_DAC_DAPLLAVC Default Description 0x0000 Left channel energy average filter coefficient setting(the coefficient [rega3[10:0],rega4] is 3.
10:0 R/W 0x0100 Gain smooth filter attack time coefficient setting(the coefficient [reg a9[10:0], reg aa] is 3.24 format 2s complement ) Reg aah_DAC DAP Low Gain Attack Time Coef Register Default: 0x0000 Bit 15:0 Read/Write R/W Register Name: AC_DAC_DAPLGATC Default Description 0x0000 Gain smooth filter attack time coefficient setting(the coefficient [reg a9[10:0], reg aa] is 3.
15:13 / / / 12:0 R/W 0x0100 The DRC gain curve offset O parameter setting(the O = [reg af[12:0], reg b0] is 5.24 format 2s complement ) Reg b0h_DAC DAP Low Gain Offset Parameter Register Default: 0x0000 Register Name: AC_DAC_DAPLGOPA Bit Read/Write Default Description 15:0 R/W 0x0000 The DRC gain curve offset O parameter setting(the K = [reg af[12:0], regb0] is 5.
0: Disable 1: Enable 12:8 R/W 0x0 Reserved 7 R/W 0x0 DAC_DRC_ENA DAC DRC enable 0: Disable 1: Enable 6:0 R/W 0x0 Reserved
