Datasheet

VS1053b Datasheet
10 VS1053B REGISTERS
SCI registers, prefix SCI_
Reg Type Reset Abbrev[bits] Description
0xC010 r 0 CHANGE[5:0] Last SCI access address
SCI_CHANGE bits
Name Bits Description
SCI_CH_WRITE 4 1 if last access was a write cycle
SCI_CH_ADDR 3:0 SCI address of last access
10.5 Serial Data Registers
SDI registers, prefix SER_
Reg Type Reset Abbrev[bits] Description
0xC011 r 0 DATA Last received 2 bytes, big-endian
0xC012 w 0 DREQ[0] DREQ pin control
10.6 DAC Registers
DAC registers, prefix DAC_
Reg Type Reset Abbrev[bits] Description
0xC013 rw 0 FCTLL DAC frequency control, 16 LSbs
0xC014 rw 0 FCTLH DAC frequency control 4MSbs, PLL control
0xC015 rw 0 LEFT DAC left channel PCM value
0xC016 rw 0 RIGHT DAC right channel PCM value
0xC045 rw 0 VOL DAC hardware volume
Every fourth clock cycle, an internal 26-bit counter is added to by (DAC_FCTLH & 15) × 65536
+ DAC_FCTLL. Whenever this counter overflows, values from DAC_LEFT and DAC_RIGHT
are read and a DAC interrupt is generated.
DAC_VOL bits
Name Bits Description
LEFT_FINE 15:12 Left channel gain +0.0 dB. . .+5.5 dB (0 to 11)
LEFT_COARSE 11:8 Left channel attenuation in -6 dB steps
RIGHT_FINE 7:4 Right channel volume +0.0 dB. . .+5.5 dB (0 to
11)
RIGHT_COARSE 3:0 Right channel attenuation in -6 dB steps
Normally DAC_VOL is handled by the firmware. DAC_VOL depends on SCI_VOL and the bass
and treble settings in SCI_BASS (and optionally SS_SWING bits in SCI_STATUS).
Version: 1.13, 2011-05-27 67