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VS1053b Datasheet

VS1053b -

Ogg Vorbis/MP3/AAC/WMA/FLAC/

MIDI AUDIO CODEC CIRCUIT

Features

• Decodes

Ogg Vorbis;

MP3 = MPEG 1 & 2 audio layer III (CBR

+VBR +ABR);

MP1/MP2 = layers I & II optional;

MPEG4 / 2 AAC-LC(+PNS),

HE-AAC v2 (Level 3) (SBR + PS);

WMA 4.0/4.1/7/8/9 all proﬁles (5-384 kbps);

General MIDI 1 / SP-MIDI format 0 ﬁles;

FLAC with software plugin;

WAV (PCM + IMA ADPCM)

• Encodes Ogg Vorbis w/ software plugin

• Encodes stereo IMA ADPCM / PCM

• Streaming support for MP3 and WAV

• EarSpeaker Spatial Processing

• Bass and treble controls

• Operates with a single 12..13 MHz clock

• Can also be used with a 24..26 MHz clock

• Internal PLL clock multiplier

• Low-power operation

• High-quality on-chip stereo DAC with no

phase error between channels

• Zero-cross detection for smooth volume

change

• Stereo earphone driver capable of driv-

ing a 30 Ω load

• Quiet power-on and power-off

• I2S interface for external DAC

• Separate voltages for analog, digital, I/O

• On-chip RAM for user code and data

• Serial control and data interfaces

• Can be used as a slave co-processor

• SPI ﬂash boot for special applications

• UART for debugging purposes

• New functions may be added with soft-

ware and upto 8 GPIO pins

• Lead-free RoHS-compliant package (Green)

Description

VS1053b is an Ogg Vorbis/MP3/AAC/WMA/

FLAC/WAVMIDI audio decoder as well as an

PCM/IMA ADPCM/Ogg Vorbis encoder on a

single chip. It contains a high-performance,

proprietary low-power DSP processor core

VS_DSP

, data memory, 16 KiB instruction

RAM and 0.5+ KiB data RAM for user appli-

cations running simultaneously with any built-

in decoder, serial control and input data in-

terfaces, upto 8 general purpose I/O pins, an

UART, as well as a high-quality variable-sample-

rate stereo ADC (mic, line, line + mic or 2×line)

and stereo DAC, followed by an earphone am-

pliﬁer and a common voltage buffer.

VS1053b receives its input bitstream through

a serial input bus, which it listens to as a

system slave. The input stream is decoded

and passed through a digital volume control

to an 18-bit oversampling, multi-bit, sigma-

delta DAC. The decoding is controlled via a

serial control bus. In addition to the basic de-

coding, it is possible to add application spe-

ciﬁc features, like DSP effects, to the user

RAM memory.

Optional factory-programmable unique chip

ID provides basis for digital rights manage-

ment or unit identiﬁcation features.

Version: 1.13, 2011-05-27 1

Summary of content (82 pages)

PAGE 1
VS1053b Datasheet VS1053b Ogg Vorbis/MP3/AAC/WMA/FLAC/ MIDI AUDIO CODEC CIRCUIT Features Description VS1053b is an Ogg Vorbis/MP3/AAC/WMA/ • Decodes FLAC/WAVMIDI audio decoder as well as an Ogg Vorbis; PCM/IMA ADPCM/Ogg Vorbis encoder on a MP3 = MPEG 1 & 2 audio layer III (CBR single chip. It contains a high-performance, +VBR +ABR); proprietary low-power DSP processor core MP1/MP2 = layers I & II optional; VS_DSP4 , data memory, 16 KiB instruction MPEG4 / 2 AAC-LC(+PNS), RAM and 0.
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VS1053b Datasheet CONTENTS Contents VS1053 1 Table of Contents 2 List of Figures 5 1 Licenses 6 2 Disclaimer 6 3 Definitions 6 4 Characteristics & Specifications 4.1 Absolute Maximum Ratings . . . . . . . . . 4.2 Recommended Operating Conditions . . . . 4.3 Analog Characteristics . . . . . . . . . . . . 4.4 Power Consumption . . . . . . . . . . . . . 4.5 Digital Characteristics . . . . . . . . . . . . . 4.6 Switching Characteristics - Boot Initialization . . . . . .
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VS1053b Datasheet 8.2 8.3 8.4 8.5 8.6 8.7 CONTENTS Supported Audio Codecs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.1 Supported MP3 (MPEG layer III) Formats . . . . . . . . . . . . . . 8.2.2 Supported MP1 (MPEG layer I) Formats . . . . . . . . . . . . . . . 8.2.3 Supported MP2 (MPEG layer II) Formats . . . . . . . . . . . . . . . 8.2.4 Supported Ogg Vorbis Formats . . . . . . . . . . . . . . . . . . . . 8.2.5 Supported AAC (ISO/IEC 13818-7 and ISO/IEC 14496-3) Formats 8.2.
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VS1053b Datasheet 9.10 Real-Time MIDI . . . . . . . . . . . . . 9.11 Extra Parameters . . . . . . . . . . . . 9.11.1 Common Parameters . . . . 9.11.2 WMA . . . . . . . . . . . . . 9.11.3 AAC . . . . . . . . . . . . . 9.11.4 Midi . . . . . . . . . . . . . . 9.11.5 Ogg Vorbis . . . . . . . . . . 9.12 SDI Tests . . . . . . . . . . . . . . . . 9.12.1 Sine Test . . . . . . . . . . . 9.12.2 Pin Test . . . . . . . . . . . 9.12.3 SCI Test . . . . . . . . . . . 9.12.4 Memory Test . . . . . . . . . 9.12.
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VS1053b Datasheet LIST OF FIGURES List of Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Pin Configuration, LQFP-48. . . . . . . . . . . . . . . . . . . . . . . . . . . VS1053b in LQFP-48 Packaging. . . . . . . . . . . . . . . . . . . . . . . . . Typical Connection Diagram Using LQFP-48. . . . . . . . . . . . . . . . . . BSYNC Signal - one byte transfer. . . . . . . . . . . . . . . . . . . . . . . . BSYNC Signal - two byte transfer. . . . . . . . . . . . . . . . . . . . . . . . SCI Word Read . . . . .
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VS1053b Datasheet 1 3 DEFINITIONS Licenses MPEG Layer-3 audio decoding technology licensed from Fraunhofer IIS and Thomson. Note: If you enable Layer I and Layer II decoding, you are liable for any patent issues that may arise from using these formats. Joint licensing of MPEG 1.0 / 2.0 Layer III does not cover all patents pertaining to layers I and II. VS1053b contains WMA decoding technology from Microsoft.
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VS1053b Datasheet 4 4 4.1 Characteristics & Specifications Absolute Maximum Ratings Parameter Analog Positive Supply Digital Positive Supply I/O Positive Supply Current at Any Non-Power Pin1 Voltage at Any Digital Input Operating Temperature Storage Temperature 1 2 CHARACTERISTICS & SPECIFICATIONS Symbol AVDD CVDD IOVDD Min -0.3 -0.3 -0.3 -0.3 -30 -65 Max 3.6 1.85 3.6 ±50 IOVDD+0.32 +85 +150 Unit V V V mA V ◦C ◦C Higher current can cause latch-up. Must not exceed 3.6 V 4.
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VS1053b Datasheet 4 4.3 CHARACTERISTICS & SPECIFICATIONS Analog Characteristics Unless otherwise noted: AVDD=3.3V, CVDD=1.8V, IOVDD=2.8V, REF=1.65V, TA=-30..+85◦ C, XTALI=12..13MHz, Internal Clock Multiplier 3.5×. DAC tested with 1307.894 Hz full-scale output sinewave, measurement bandwidth 20..20000 Hz, analog output load: LEFT to GBUF 30 Ω, RIGHT to GBUF 30 Ω. Microphone test amplitude 48 mVpp, fs =1 kHz, Line input test amplitude 1.26 V, fs =1 kHz.
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VS1053b Datasheet 4 4.4 CHARACTERISTICS & SPECIFICATIONS Power Consumption Tested with an Ogg Vorbis 128 kbps sample and generated sine. Output at full volume. Internal clock multiplier 3.0×. TA=+25◦ C. Parameter Power Supply Consumption AVDD, Reset Power Supply Consumption CVDD = 1.8V, Reset Power Supply Consumption AVDD, sine test, 30 Ω + GBUF Power Supply Consumption CVDD = 1.
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VS1053b Datasheet 5 5 PACKAGES AND PIN DESCRIPTIONS Packages and Pin Descriptions 5.1 Packages LPQFP-48 is a lead (Pb) free and also RoHS compliant package. RoHS is a short name of Directive 2002/95/EC on the restriction of the use of certain hazardous substances in electrical and electronic equipment. 5.1.1 LQFP-48 48 1 Figure 1: Pin Configuration, LQFP-48. LQFP-48 package dimensions are at http://www.vlsi.fi/ . Figure 2: VS1053b in LQFP-48 Packaging. Version: 1.
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VS1053b Datasheet 5 Pad Name MICP / LINE1 MICN XRESET DGND0 CVDD0 IOVDD0 CVDD1 DREQ GPIO2 / DCLK1 GPIO3 / SDATA1 GPIO6 / I2S_SCLK3 GPIO7 / I2S_SDATA3 XDCS / BSYNC1 IOVDD1 VCO DGND1 XTALO XTALI IOVDD2 DGND2 DGND3 DGND4 XCS CVDD2 GPIO5 / I2S_MCLK3 RX TX SCLK SI SO CVDD3 XTEST GPIO0 GPIO1 GND GPIO4 I2S_LROUT3 AGND0 AVDD0 RIGHT AGND1 AGND2 GBUF AVDD1 RCAP AVDD2 LEFT AGND3 LINE2 / PACKAGES AND PIN DESCRIPTIONS LQFP Pin 1 2 3 4 5 6 7 8 9 10 11 12 Pin Type AI AI DI DGND CPWR IOPWR CPWR DO DIO DIO DIO DIO Fun
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VS1053b Datasheet 5 PACKAGES AND PIN DESCRIPTIONS 1 First pin function is active in New Mode, latter in Compatibility Mode. 2 Unless pull-down resistor is used, SPI Boot is tried. See Chapter 9.9 for details. 3 If I2S_CF_ENA is ’0’ the pins are used for GPIO. See Chapter 10.13 for details. Pin types: Type DI DO DIO DO3 AI Description Digital input, CMOS Input Pad Digital output, CMOS Input Pad Digital input/output Digital output, CMOS Tri-stated Output Pad Analog input Version: 1.
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VS1053b Datasheet 6 6 CONNECTION DIAGRAM, LQFP-48 Connection Diagram, LQFP-48 Figure 3: Typical Connection Diagram Using LQFP-48. Figure 3 shows a typical connection diagram for VS1053. Figure Note 1: Connect either Microphone In or Line In, but not both at the same time. Note: This connection assumes SM_SDINEW is active (see Chapter 8.7.1). If also SM_SDISHARE is used, xDCS should be tied low or high (see Chapter 7.2.1). Version: 1.
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VS1053b Datasheet 6 CONNECTION DIAGRAM, LQFP-48 The common buffer GBUF can be used for common voltage (1.23 V) for earphones. This will eliminate the need for large isolation capacitors on line outputs, and thus the audio output pins from VS1053b may be connected directly to the earphone connector. GBUF must NOT be connected to ground under any circumstances. If GBUF is not used, LEFT and RIGHT must be provided with coupling capacitors.
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VS1053b Datasheet 7 7 SPI BUSES SPI Buses 7.1 General The SPI Bus - that was originally used in some Motorola devices - has been used for both VS1053b’s Serial Data Interface SDI (Chapters 7.4 and 8.5) and Serial Control Interface SCI (Chapters 7.5 and 8.6). 7.2 SPI Bus Pin Descriptions 7.2.1 VS1002 Native Modes (New Mode) These modes are active on VS1053b when SM_SDINEW is set to 1 (default at startup).
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VS1053b Datasheet SDI Pin - SCI Pin XCS BSYNC DCLK SCK SDATA - SI SO 7.3 7 SPI BUSES Description Active low chip select input. A high level forces the serial interface into standby mode, ending the current operation. A high level also forces serial output (SO) to high impedance state. SDI data is synchronized with a rising edge of BSYNC. Serial clock input. The serial clock is also used internally as the master clock for the register interface. SCK can be gated or continuous.
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VS1053b Datasheet 7 SPI BUSES MSb or LSb first, depending of contents of SCI_MODE (Chapter 8.7.1). The firmware is able to accept the maximum bitrate the SDI supports. 7.4.2 SDI in VS1002 Native Modes (New Mode) In VS1002 native modes (SM_NEWMODE is 1), byte synchronization is achieved by XDCS. The state of XDCS may not change while a data byte transfer is in progress.
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VS1053b Datasheet 7.4.3 7 SPI BUSES SDI in VS1001 Compatibility Mode (deprecated) BSYNC SDATA D7 D6 D5 D4 D3 D2 D1 D0 DCLK Figure 4: BSYNC Signal - one byte transfer. When VS1053b is running in VS1001 compatibility mode, a BSYNC signal must be generated to ensure correct bit-alignment of the input bitstream.
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VS1053b Datasheet 7.5.2 7 SPI BUSES SCI Read XCS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 0 0 0 0 0 0 1 1 0 0 0 30 31 SCK 3 SI instruction (read) 2 1 0 don’t care 0 data out address 15 14 SO 0 0 0 0 0 0 0 0 0 0 0 0 0 don’t care 0 0 1 0 0 X execution DREQ Figure 6: SCI Word Read VS1053b registers are read from using the following sequence, as shown in Figure 6. First, XCS line is pulled low to select the device.
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VS1053b Datasheet 7 SPI BUSES SI line followed by an 8-bit word address. After the word has been shifted in and the last clock has been sent, XCS should be pulled high to end the WRITE sequence. After the last bit has been sent, DREQ is driven low for the duration of the register update, marked “execution” in the figure. The time varies depending on the register and its contents (see table in Chapter 8.7 for details).
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VS1053b Datasheet 7.6 7 SPI BUSES SPI Timing Diagram tWL tXCSS tWH tXCSH XCS tXCS 0 1 14 15 30 16 31 SCK SI tH tSU SO tZ tV tDIS Figure 9: SPI Timing Diagram. Symbol tXCSS tSU tH tZ tWL tWH tV tXCSH tXCS tDIS 1 Min 5 0 2 0 2 2 2 (+ 25 ns1 ) 1 2 Max 10 Unit ns ns CLKI cycles ns CLKI cycles CLKI cycles CLKI cycles CLKI cycles CLKI cycles ns 25 ns is when pin loaded with 100 pF capacitance. The time is shorter with lower capacitance.
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VS1053b Datasheet 7.7 7.7.1 7 SPI BUSES SPI Examples with SM_SDINEW and SM_SDISHARED set Two SCI Writes SCI Write 1 SCI Write 2 XCS 0 1 2 3 30 31 1 0 32 33 61 62 63 2 1 0 SCK SI 0 0 0 X 0 0 X 0 DREQ up before finishing next SCI write DREQ Figure 10: Two SCI Operations. Figure 10 shows two consecutive SCI operations. Note that xCS must be raised to inactive state between the writes. Also DREQ must be respected as shown in the figure. 7.7.
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VS1053b Datasheet 7.7.3 7 SPI BUSES SCI Operation in Middle of Two SDI Bytes SDI Byte SDI Byte SCI Operation XCS 0 7 1 8 9 39 40 41 7 6 46 47 1 0 SCK 7 6 5 1 0 0 SI 5 X 0 DREQ high before end of next transfer DREQ Figure 12: Two SDI Bytes Separated By an SCI Operation. Figure 12 shows how an SCI operation is embedded in between SDI operations. xCS edges are used to synchronize both SDI and SCI. Remember to respect DREQ as shown in the figure. Version: 1.
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VS1053b Datasheet 8 8 FUNCTIONAL DESCRIPTION Functional Description 8.1 Main Features VS1053b is based on a proprietary digital signal processor, VS_DSP. It contains all the code and data memory needed for Ogg Vorbis, MP3, AAC, WMA and WAV PCM + ADPCM audio decoding and a MIDI synthesizer, together with serial interfaces, a multirate stereo audio DAC and analog output amplifiers and filters.
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VS1053b Datasheet 8 8.2.2 FUNCTIONAL DESCRIPTION Supported MP1 (MPEG layer I) Formats Note: Layer I / II decoding must be specifically enabled from register SCI_MODE. MPEG 1.
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VS1053b Datasheet 8 8.2.5 FUNCTIONAL DESCRIPTION Supported AAC (ISO/IEC 13818-7 and ISO/IEC 14496-3) Formats VS1053b decodes MPEG2-AAC-LC-2.0.0.0 and MPEG4-AAC-LC-2.0.0.0 streams, i.e. the low complexity profile with maximum of two channels can be decoded. If a stream contains more than one element and/or element type, you can select which one to decode from the 16 singlechannel, 16 channel-pair, and 16 low-frequency elements. The default is to select the first one that appears in the stream.
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VS1053b Datasheet 8 FUNCTIONAL DESCRIPTION mdat atom last in the file, and thus suitable for web servers’ audio streaming. You can use this kind of tool to process files for VS1053b too. For example mp4creator -optimize file.mp4.
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VS1053b Datasheet 8 8.2.6 FUNCTIONAL DESCRIPTION Supported WMA Formats Windows Media Audio codec versions 2, 7, 8, and 9 are supported. All WMA profiles (L1, L2, and L3) are supported. Previously streams were separated into Classes 1, 2a, 2b, and 3. The decoder has passed Microsoft’s conformance testing program. Windows Media Audio Professional is a different codec and is not supported. WMA 4.0 / 4.
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VS1053b Datasheet 8 8.2.7 FUNCTIONAL DESCRIPTION Supported FLAC Formats Upto 48 kHz and 24-bit FLAC files are supported with the VS1053b Patches w/ FLAC Decoder plugin that is available at http://www.vlsi.fi/en/support/software/vs10xxplugins.html . Read the accompanying documentation of the plugin for details. 8.2.8 Supported RIFF WAV Formats The most common RIFF WAV subformats are supported, with 1 or 2 audio channels.
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VS1053b Datasheet 8 8.2.9 FUNCTIONAL DESCRIPTION Supported MIDI Formats General MIDI and SP-MIDI format 0 files are played. Format 1 and 2 files must be converted to format 0 by the user. The maximum polyphony is 64, the maximum sustained polyphony is 40.
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VS1053b Datasheet 8 1 Acoustic Grand Piano 2 Bright Acoustic Piano 3 Electric Grand Piano 4 Honky-tonk Piano 5 Electric Piano 1 6 Electric Piano 2 7 Harpsichord 8 Clavi 9 Celesta 10 Glockenspiel 11 Music Box 12 Vibraphone 13 Marimba 14 Xylophone 15 Tubular Bells 16 Dulcimer 17 Drawbar Organ 18 Percussive Organ 19 Rock Organ 20 Church Organ 21 Reed Organ 22 Accordion 23 Harmonica 24 Tango Accordion 25 Acoustic Guitar (nylon) 26 Acoustic Guitar (steel) 27 Electric Guitar (jazz) 28 Electric Guitar (clean) 29
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VS1053b Datasheet 8 8.3 FUNCTIONAL DESCRIPTION Data Flow of VS1053b SDI Bitstream FIFO MP3 MP2 MP1 WAV ADPCM WMA AAC MIDI Vorbis SM_ADPCM=0 SB_AMPLITUDE=0 AIADDR = 0 Bass enhancer User Application Treble control SB_AMPLITUDE!=0 AIADDR != 0 Audio FIFO 2048 stereo samples ST_AMPLITUDE=0 Ear Speaker ST_AMPLITUDE!=0 L S.rate.conv. R and DAC Volume SCI_VOL control Figure 13: Data Flow of VS1053b.
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VS1053b Datasheet 8 8.4 FUNCTIONAL DESCRIPTION EarSpeaker Spatial Processing While listening to headphones the sound has a tendency to be localized inside the head. The sound field becomes flat and lacking the sensation of dimensions. This is an unnatural, awkward and sometimes even disturbing situation. This phenomenon is often referred in literature as ‘lateralization’, meaning ’in-the-head’ localization. Long-term listening to lateralized sound may lead to listening fatigue.
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VS1053b Datasheet 8 FUNCTIONAL DESCRIPTION • normal: Suited for listening to normal musical scores with headphones, moves sound source further away than minimal. • extreme: Suited for old or ’dry’ recordings, or if the audio to be played is artificial, for example generated MIDI. 8.5 Serial Data Interface (SDI) The serial data interface is meant for transferring compressed data for the different decoders of VS1053b.
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VS1053b Datasheet 8 8.7 FUNCTIONAL DESCRIPTION SCI Registers VS1053b sets DREQ low when it detects an SCI operation (this delay is 16 to 40 CLKI cycles depending on whether an interrupt service routine is active) and restores it when it has processed the operation. The duration depends on the operation. If DREQ is low when an SCI operation is performed, it also stays low after SCI operation processing.
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VS1053b Datasheet 8 8.7.1 FUNCTIONAL DESCRIPTION SCI_MODE (RW) SCI_MODE is used to control the operation of VS1053b and defaults to 0x0800 (SM_SDINEW set).
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VS1053b Datasheet 8 FUNCTIONAL DESCRIPTION Bits SM_EARSPEAKER_LO and SM_EARSPEAKER_HI control the EarSpeaker spatial processing. If both are 0, the processing is not active. Other combinations activate the processing and select 3 different effect levels: LO = 1, HI = 0 selects minimal, LO = 0, HI = 1 selects normal, and LO = 1, HI = 1 selects extreme. EarSpeaker takes approximately 12 MIPS at 44.1 kHz samplerate. If SM_TESTS is set, SDI tests are allowed. For more details on SDI tests, look at Chapter 9.
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VS1053b Datasheet 8 8.7.2 FUNCTIONAL DESCRIPTION SCI_STATUS (RW) SCI_STATUS contains information on the current status of VS1053b. It also controls some low-level things that the user does not usually have to care about. Name SS_DO_NOT_JUMP SS_SWING SS_VCM_OVERLOAD SS_VCM_DISABLE SS_VER SS_APDOWN2 SS_APDOWN1 SS_AD_CLOCK SS_REFERENCE_SEL Bits 15 14:12 11 10 9:8 7:4 3 2 1 0 Description Header in decode, do not fast forward/rewind Set swing to +0 dB, +0.5 dB, .., or +3.
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VS1053b Datasheet 8 8.7.3 FUNCTIONAL DESCRIPTION SCI_BASS (RW) Name ST_AMPLITUDE ST_FREQLIMIT SB_AMPLITUDE SB_FREQLIMIT Bits 15:12 11:8 7:4 3:0 Description Treble Control in 1.5 dB steps (-8..7, 0 = off) Lower limit frequency in 1000 Hz steps (1..15) Bass Enhancement in 1 dB steps (0..15, 0 = off) Lower limit frequency in 10 Hz steps (2..15) The Bass Enhancer VSBE is a powerful bass boosting DSP algorithm, which tries to take the most out of the users earphones without causing clipping.
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VS1053b Datasheet 8 8.7.4 FUNCTIONAL DESCRIPTION SCI_CLOCKF (RW) The operation of SCI_CLOCKF has changed slightly in VS1053b compared to VS1003 and VS1033. Multiplier 1.5× and addition 0.5× have been removed to allow higher clocks to be configured. Name SC_MULT SC_ADD SC_FREQ SCI_CLOCKF bits Bits Description 15:13 Clock multiplier 12:11 Allowed multiplier addition 10: 0 Clock frequency SC_MULT activates the built-in clock multiplier. This will multiply XTALI to create a higher CLKI.
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VS1053b Datasheet 8 FUNCTIONAL DESCRIPTION This means that XTALI = 1000 × 4000 + 8000000 = 12 MHz. The clock multiplier is set to 3.5×XTALI = 42 MHz, and the maximum allowed multiplier that the firmware may automatically choose to use is (3.5 + 1.0)×XTALI = 54 MHz. 8.7.5 SCI_DECODE_TIME (RW) When decoding correct data, current decoded time is shown in this register in full seconds. The user may change the value of this register.
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VS1053b Datasheet 8 8.7.8 FUNCTIONAL DESCRIPTION SCI_WRAMADDR (W) SCI_WRAMADDR is used to set the program address for following SCI_WRAM writes/reads. Use an address offset from the following table to access X, Y, I or peripheral memory. WRAMADDR Start. . . End 0x1800. . . 0x18XX 0x5800. . . 0x58XX 0x8040. . . 0x84FF 0xC000. . . 0xFFFF Dest. addr. Start. . . End 0x1800. . . 0x18XX 0x1800. . . 0x18XX 0x0040. . . 0x04FF 0xC000. . .
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VS1053b Datasheet 8 Bit HDAT1[15:5] HDAT1[4:3] Function syncword ID HDAT1[2:1] layer HDAT1[0] protect bit HDAT0[15:12] HDAT0[11:10] bitrate samplerate HDAT0[9] pad bit HDAT0[8] HDAT0[7:6] private bit mode HDAT0[5:4] HDAT0[3] extension copyright HDAT0[2] original HDAT0[1:0] emphasis Value 2047 3 2 1 0 3 2 1 0 1 0 3 2 1 0 1 0 3 2 1 0 1 0 1 0 3 2 1 0 FUNCTIONAL DESCRIPTION Explanation stream valid ISO 11172-3 MPG 1.0 ISO 13818-3 MPG 2.0 (1/2-rate) MPG 2.5 (1/4-rate) MPG 2.
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VS1053b Datasheet 8 “bitrate” 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Layer I ID=3 ID=0,1,2 kbit/s forbidden forbidden 448 256 416 224 384 192 352 176 320 160 288 144 256 128 224 112 192 96 160 80 128 64 96 56 64 48 32 32 - Layer II ID=3 ID=0,1,2 kbit/s forbidden forbidden 384 160 320 144 256 128 224 112 192 96 160 80 128 64 112 56 96 48 80 40 64 32 56 24 48 16 32 8 - FUNCTIONAL DESCRIPTION Layer III ID=3 ID=0,1,2 kbit/s forbidden forbidden 320 160 256 144 224 128 192 112 160 96 128 80 112 64 96 56 80 48
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VS1053b Datasheet 8 8.7.11 FUNCTIONAL DESCRIPTION SCI_VOL (RW) SCI_VOL is a volume control for the player hardware. The most significant byte of the volume register controls the left channel volume, the low part controls the right channel volume. The channel volume sets the attenuation from the maximum volume level in 0.5 dB steps. Thus, maximum volume is 0x0000 and total silence is 0xFEFE. Note, that after hardware reset the volume is set to full volume.
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VS1053b Datasheet 9 9.1 9 OPERATION Operation Clocking VS1053b operates on a single, nominally 12.288 MHz fundamental frequency master clock. This clock can be generated by external circuitry (connected to pin XTALI) or by the internal clock crystal interface (pins XTALI and XTALO). This clock is used by the analog parts and determines the highest available samplerate. With 12.288 MHz clock all samplerates upto 48000 Hz are available. VS1053b can also use 24..
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VS1053b Datasheet 9 OPERATION will stay down for about 22000 clock cycles, which means an approximate 1.8 ms delay if VS1053b is run at 12.288 MHz. After DREQ is up, you may continue playback as usual. As opposed to all earlier VS10XX chips, it is not recommended to do a software reset between songs. This way the user may be sure that even files with low samplerates or bitrates are played right to their end. 9.
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VS1053b Datasheet 9.5.1 9 OPERATION Playing a Whole File This is the default playback mode. 1. 2. 3. 4. 5. 6. Send an audio file to VS1053b. Read extra parameter value endFillByte (Chapter 9.11). Send at least 2052 bytes of endFillByte[7:0]. Set SCI_MODE bit SM_CANCEL. Send at least 32 bytes of endFillByte[7:0]. Read SCI_MODE. If SM_CANCEL is still set, go to 5. If SM_CANCEL hasn’t cleared after sending 2048 bytes, do a software reset (this should be extremely rare). 7.
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VS1053b Datasheet 9.5.4 9 OPERATION Fast Forward and Rewind without Audio To do fast forward and rewind you need the capability to do random access to the audio file. Unfortunately fast forward and rewind isn’t available at all times, like when file headers are being read. 1. Send a portion of an audio file to VS1053b. 2. When random access is required, read SCI_STATUS bit SS_DO_NOT_JUMP. If that bit is set, random access cannot be performed, so go back to 1. 3.
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VS1053b Datasheet 9.6 9 OPERATION Feeding PCM data VS1053b can be used as a PCM decoder by sending a WAV file header. If the length sent in the WAV header is 0xFFFFFFFF, VS1053b will stay in PCM mode indefinitely (or until SM_CANCEL has been set). 8-bit linear and 16-bit linear audio is supported in mono or stereo.
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VS1053b Datasheet 9.8 9 OPERATION PCM/ADPCM Recording This chapter explains how to create RIFF/WAV file in PCM or IMA ADPCM format. IME ADPCM is a widely supported ADPCM format and many PC audio playback programs can play it. IMA ADPCM recording gives roughly a compression ratio of 4:1 compared to linear, 16-bit audio. This makes it possible to record for example ono 8 kHz audio at 32.44 kbit/s.
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VS1053b Datasheet 9 OPERATION WriteVS10xxPatch() should perform the following SCI writes (only for VS1053b and VS8053b): Register SCI_WRAMADDR SCI_WRAM SCI_WRAM SCI_WRAM SCI_WRAM SCI_WRAM SCI_WRAM SCI_WRAM SCI_WRAM SCI_WRAM SCI_WRAM SCI_WRAM SCI_WRAM SCI_WRAM SCI_WRAM SCI_WRAM SCI_WRAM SCI_WRAM SCI_WRAM SCI_WRAM SCI_WRAM SCI_WRAM SCI_WRAM SCI_WRAM SCI_WRAM SCI_WRAM SCI_WRAM SCI_WRAM SCI_WRAM SCI_WRAMADDR SCI_WRAM SCI_WRAM Reg.
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VS1053b Datasheet 9 OPERATION IMA ADPCM block is 256 words, i.e. 512 bytes. If you wish to interrupt reading data and possibly continue later, please stop at the boundary. This way whole blocks are skipped and the encoded stream stays valid. 9.8.3 Adding a PCM RIFF Header To make your PCM file a RIFF / WAV file, you have to add a header to the data. The following shows a header for a mono file. Note that 2- and 4-byte values are little-endian (lowest byte first).
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VS1053b Datasheet 9.8.4 9 OPERATION Adding an IMA ADPCM RIFF Header To make your IMA ADPCM file a RIFF / WAV file, you have to add a header to the data. The following shows a header for a mono file. Note that 2- and 4-byte values are little-endian (lowest byte first).
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VS1053b Datasheet 0000 0010 0020 0030 9.8.5 52 14 00 14 49 00 02 15 46 00 04 97 46 00 00 00 34 11 02 64 2e 00 00 61 99 02 f9 74 00 00 01 61 57 44 66 00 41 ac 61 2e 56 00 63 99 9 OPERATION 45 66 6d 74 20 |RIFF4...WAVEfmt | 00 a7 ae 00 00 |........D.......| 74 04 00 00 00 |........fact....| 00 |....data....| Playing ADPCM Data In order to play back your PCM / IMA ADPCM recordings, you have to have a file with a header as described in Chapter 9.8.3 or Chapter 9.8.4.
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VS1053b Datasheet dB -0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 -4.5 -5.0 -5.5 -6.0 DAC_VOL 0x0000 0xb1b1 0xa1a1 0x9191 0x8181 0x7171 0x6161 0x5151 0x4141 0x3131 0x2121 0x1111 0x0101 dB -6.5 : -12.0 -12.5 : -18.0 -18.5 : -24.0 -24.5 : -30.0 -30.5 Version: 1.13, 2011-05-27 DAC_VOL 0xb2b2 : 0x0202 0xb3b3 : 0x0303 0xb4b4 : 0x0404 0xb5b5 : 0x0505 0xb6b6 dB : -36.0 -36.5 : -42.0 -42.5 : -48.0 -48.5 : -54.0 -54.5 : DAC_VOL : 0x0606 0xb7b7 : 0x0707 0xb8b8 : 0x0808 0xb9b9 : 0x0909 0xbaba : dB -60.0 -60.
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VS1053b Datasheet 9.9 9 OPERATION SPI Boot If GPIO0 is set with a pull-up resistor to 1 at boot time, VS1053b tries to boot from external SPI memory. SPI boot redefines the following pins: Normal Mode GPIO0 GPIO1 DREQ GPIO2 SPI Boot Mode xCS CLK MOSI MISO The memory has to be an SPI Bus Serial EEPROM with 16-bit or 24-bit addresses. The serial speed used by VS1053b is 245 kHz with the nominal 12.288 MHz clock. The first three bytes in the memory have to be 0x50, 0x26, 0x48. 9.
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VS1053b Datasheet 9.11 9 OPERATION Extra Parameters The following structure is in X memory at address 0x1e02 (note the different location than in VS1033) and can be used to change some extra parameters or get useful information.
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VS1053b Datasheet 9 OPERATION You can see that in the invalid read the low part wraps from 0x0000 to 0xffff while the high part stays the same. In this case the second read gives a valid answer, otherwise always use the value of the first read. The second read is needed when it is possible that the low part wraps around, changing the high part, i.e. when the low part is small. bytesLeft is only decreased by one at a time, so a reread is needed only if the low part is 0. 9.11.
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VS1053b Datasheet 9 OPERATION implement perfect fast forward and rewind for WMA and AAC (ADIF, .mp4 / .m4a). positionMsec is a field that gives the current play position in a file in milliseconds, regardless of rewind and fast forward operations. The value is only available in codecs that can determine the play position from the stream itself. Currently WMA and Ogg Vorbis provide this information. If the position is unknown, this field contains -1.
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VS1053b Datasheet 9.11.3 9 OPERATION AAC Parameter config1 sceFoundMask cpeFoundMask lfeFoundMask playSelect dynCompress dynBoost sbrAndPsStatus Address 0x1e03(7:4) 0x1e2a 0x1e2b 0x1e2c 0x1e2d 0x1e2e 0x1e2f 0x1e30 Usage SBR and PS select Single channel elements found Channel pair elements found Low frequency elements found Play element selection Compress coefficient for DRC, -8192=1.0 Boost coefficient for DRC, 8192=1.
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VS1053b Datasheet config1(7:6) ’00’ ’01’ ’10’ ’11’ 9 OPERATION Usage normal mode, process PS if it is available process PS if it is available, but in downsampled mode reserved disable PS processing AAC decoder can also increase the internal clock automatically when it detects that a file can not be decoded correctly with the current clock. The maximum allowed clock is configured with the SCI_CLOCKF register.
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VS1053b Datasheet 9 OPERATION For example gain = -11 means that volume should be decreased by 5.5 dB (−11/2 = −5.5), and left and right attenuation should be increased by 11. When gain = 2 volume should be increased by 1 dB (2/2 = 1.0), and left and right attenuation should be decreased by 2. Because volume setting can not go above +0 dB, the value should be saturated. Gain -11 (-5.5 dB) -11 (-5.5 dB) +2 (+1.0 dB) +2 (+1.0 dB) +2 (+1.0 dB) 9.12 Volume 0 (+0.0 dB) 3 (-1.5 dB) 0 (+0.0 dB) 1 (-0.
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VS1053b Datasheet 9.12.2 9 OPERATION Pin Test Pin test is activated with the 8-byte sequence 0x50 0xED 0x6E 0x54 0 0 0 0. This test is meant for chip production testing only. 9.12.3 SCI Test Sci test is initialized with the 8-byte sequence 0x53 0x70 0xEE n 0 0 0 0, where n is the register number to test. The content of the given register is read and copied to SCI_HDAT0. If the register to be tested is HDAT0, the result is copied to SCI_HDAT1.
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VS1053b Datasheet 9 OPERATION volume (SCI_VOL), and samplerate (SCI_AUDATA) can be set before or during the test. Write 0x4020 to SCI_AIADDR to start the test. SCI_AICTRLn can be calculated from the desired frequency and DAC samplerate by: SCI_AICT RLn = Fsin × 65536/Fs The maximum value for SCI_AICTRLn is 0x8000U. For the best S/N ratio for the generated sine, three LSb’s of the SCI_AICTRLn should be zero.
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VS1053b Datasheet 10 10 10.1 VS1053B REGISTERS VS1053b Registers Who Needs to Read This Chapter User software is required when a user wishes to add some own functionality like DSP effects to VS1053b. However, most users of VS1053b don’t need to worry about writing their own code, or about this chapter, including those who only download software plug-ins from VLSI Solution’s Web site. Note: Also see VS1063 Hardware Guide for more information, because the hardware is compatible with VS1053. 10.
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VS1053b Datasheet 10 Reg 0xC010 Type r Reset 0 Serial Data Registers Reg 0xC011 0xC012 10.6 SCI registers, prefix SCI_ Abbrev[bits] Description CHANGE[5:0] Last SCI access address SCI_CHANGE bits Bits Description 4 1 if last access was a write cycle 3:0 SCI address of last access Name SCI_CH_WRITE SCI_CH_ADDR 10.
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VS1053b Datasheet 10 10.7 VS1053B REGISTERS GPIO Registers Reg 0xC017 0xC018 0xC019 Type rw r rw Reset 0 0 0 GPIO registers, prefix GPIO_ Abbrev[bits] Description DDR[7:0] Direction IDATA[11:0] Values read from the pins ODATA[7:0] Values set to the pins GPIO_DIR is used to set the direction of the GPIO pins. 1 means output. GPIO_ODATA remembers its values even if a GPIO_DIR bit is set to input. GPIO_IDATA is used to read the pin states.
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VS1053b Datasheet 10 10.8 VS1053B REGISTERS Interrupt Registers Reg 0xC01A 0xC01B 0xC01C 0xC01D Type rw w w rw Reset 0 0 0 0 Interrupt registers, prefix INT_ Abbrev[bits] Description ENABLE[7:0] Interrupt enable GLOB_DIS[-] Write to add to interrupt counter GLOB_ENA[-] Write to subtract from interrupt counter COUNTER[4:0] Interrupt counter INT_ENABLE controls the interrupts.
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VS1053b Datasheet 10 10.9 VS1053B REGISTERS Watchdog v1.0 2002-08-26 The watchdog consist of a watchdog counter and some logic. After reset, the watchdog is inactive. The counter reload value can be set by writing to WDOG_CONFIG. The watchdog is activated by writing 0x4ea9 to register WDOG_RESET. Every time this is done, the watchdog counter is reset. Every 65536’th clock cycle the counter is decremented by one. If the counter underflows, it will activate vsdsp’s internal reset sequence.
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VS1053b Datasheet 10 10.10 VS1053B REGISTERS UART v1.1 2004-10-09 RS232 UART implements a serial interface using rs232 standard. Start bit D0 D1 D2 D3 D4 D5 D6 Stop D7 bit Figure 15: RS232 Serial Interface Protocol When the line is idling, it stays in logic high state. When a byte is transmitted, the transmission begins with a start bit (logic zero) and continues with data bits (LSB first) and ends up with a stop bit (logic high). 10 bits are sent for each 8-bit byte frame. 10.10.
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VS1053b Datasheet 10 VS1053B REGISTERS UART_ST_TXRUNNING is set if the transmitter shift register is in operation. 10.10.3 Data UARTx_DATA A read from UARTx_DATA returns the received byte in bits 7:0, bits 15:8 are returned as ’0’. If there is no more data to be read, the receiver data register full indicator will be cleared. A receive interrupt will be generated when a byte is moved from the receiver shift register to the receiver data register. A write to UARTx_DATA sets a byte for transmission.
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VS1053b Datasheet 10 VS1053B REGISTERS Example UART Speeds, fm = 26M Hz Comm. Speed [bps] UART_DIV_D1 UART_DIV_D2 4800 85 63 9600 42 63 14400 42 42 19200 51 26 28800 42 21 38400 25 26 57600 1 226 115200 0 226 10.10.6 Interrupts and Operation Transmitter operates as follows: After an 8-bit word is written to the transmit data register it will be transmitted instantly if the transmitter is not busy transmitting the previous byte. When the transmission begins a TX_INTR interrupt will be sent.
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VS1053b Datasheet 10 10.11 VS1053B REGISTERS Timers v1.0 2002-04-23 There are two 32-bit timers that can be initialized and enabled independently of each other. If enabled, a timer initializes to its start value, written by a processor, and starts decrementing every clock cycle. When the value goes past zero, an interrupt is sent, and the timer initializes to the value in its start value register, and continues downcounting. A timer stays in that loop as long as it is enabled.
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VS1053b Datasheet 10 10.11.3 Configuration TIMER_ENABLE Name TIMER_EN_T1 TIMER_EN_T0 10.11.4 VS1053B REGISTERS TIMER_ENABLE Bits Bits Description 1 Enable timer 1 0 Enable timer 0 Timer X Startvalue TIMER_Tx[L/H] The 32-bit start value TIMER_Tx[L/H] sets the initial counter value when the timer is reset. The fi timer interrupt frequency ft = c+1 where fi is the master clock obtained with the clock divider (see Chapter 10.11.2 and c is TIMER_Tx[L/H].
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VS1053b Datasheet 10 10.12 VS1053B REGISTERS VS1053b Audio Path MICN MICP LINE1 MIC AMP ADC MUX Stereo ADC LINE2 Audio FIFO Sample-Rate Converter Sigma-Delta Modulator + Analog Drivers LEFT RIGHT CBUF Volume Control SRC I2S SDM Figure 16: VS1053b ADC and DAC data paths In PCM / IMA ADPCM encoding mode the data from Analog-to-Digital conversion is first processed in 48 kHz or 24 kHz samplerate.
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VS1053b Datasheet 10 10.13 VS1053B REGISTERS I2S DAC Interface The I2S Interface makes it possible to attach an external DAC to the system. Note: The sample rate of the audio file and the I2S rate are independent. All audio will be automatically converted to 6.144 MHz for VS1053 DAC and to the configured I2S rate using a high-quality sample-rate converter. Note: In VS1053b the I2S pins share different GPIO pins than in VS1033 to be able to use SPI boot and I2S in the same application. 10.13.
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VS1053b Datasheet 10 VS1053B REGISTERS To enable I2S first write 0xc017 to SCI_WRAMADDR and 0xf0 to SCI_WRAM, then write 0xc040 to SCI_WRAMADDR and 0x0c to SCI_WRAM. See application notes for more information. Version: 1.
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VS1053b Datasheet 11 11 VERSION CHANGES Version Changes This chapter describes the lastest and most important changes done to VS1053b 11.1 Changes Between VS1033c and VS1053a/b Firmware, 2007-03-08 Completely new or major changes: • I2S pins are now in GPIO4-GPIO7 and do not overlap with SPI boot pins. • No software reset required between files when used correctly. • Ogg Vorbis decoding added. Non-fatal ogg or vorbis decode errors cause automatic resync. This allows easy rewind and fast forward.
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VS1053b Datasheet 11 VERSION CHANGES • Read and write to YRAM at 0xe000..0xffff added to SCI_WRAMADDR/SCI_WRAM. • The resync parameter (parametric_x.resync) is set to 32767 after reset to allow inifinite resynchronization attempts (or until SM_CANCEL is set). Old operation can be restored by writing 0 to resync after reset. • WMA,AAC: more robust resync. • WMA,AAC: If resync is performed, broadcast mode is automatically activated.
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VS1053b Datasheet 12 12 DOCUMENT VERSION CHANGES Document Version Changes This chapter describes the most important changes to this document. Version 1.13, 2011-05-27 • xRESET, XTALI and XTALO high-level are referenced from IOVDD in Chapter 4.5. Version 1.12, 2010-10-28 • Fixed the real-time MIDI through SDI documentation. Version 1.11 for VS8053b, 2010-04-30 • Minor updates. Version 1.10 for VS1053b, 2009-09-04 • Added mentions of new Ogg Vorbis encoder and FLAC decoder plugins.
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VS1053b Datasheet 13 13 CONTACT INFORMATION Contact Information VLSI Solution Oy Entrance G, 2nd floor Hermiankatu 8 FI-33720 Tampere FINLAND Fax: +358-3-3140-8288 Phone: +358-3-3140-8200 Email: sales@vlsi.fi URL: http://www.vlsi.fi/ Version: 1.