Datasheet

Register description LSM6DS3
76/99 DocID026899 Rev 7
9.74 INT_DUR2 (5Ah)
Tap recognition function setting register (r/w).
9.75 WAKE_UP_THS (5Bh)
Single and double-tap function threshold register (r/w).
Table 179. Threshold for D4D/D6D function
SIXD_THS[1:0] Threshold value
00 80 degrees
01 70 degrees
10 60 degrees
11 50 degrees
Table 180. INT_DUR2 register
DUR3 DUR2 DUR1 DUR0 QUIET1 QUIET0 SHOCK1 SHOCK0
Table 181. INT_DUR2 register description
DUR[3:0]
Duration of maximum time gap for double tap recognition. Default: 0000
When double tap recognition is enabled, this register expresses the maximum time
between two consecutive detected taps to determine a double tap event. The
default value of these bits is 0000b which corresponds to 16*ODR_XL time. If the
DUR[3:0] bits are set to a different value, 1LSB corresponds to 32*ODR_XL time.
QUIET[1:0]
Expected quiet time after a tap detection. Default value: 00
Quiet time is the time after the first detected tap in which there must not be any
overthreshold event. The default value of these bits is 00b which corresponds to
2*ODR_XL time. If the QUIET[1:0] bits are set to a different value, 1LSB
corresponds to 4*ODR_XL time.
SHOCK[1:0]
Maximum duration of overthreshold event. Default value: 00
Maximum duration is the maximum time of an overthreshold signal detection to be
recognized as a tap event. The default value of these bits is 00b which corresponds
to 4*ODR_XL time. If the SHOCK[1:0] bits are set to a different value, 1LSB
corresponds to 8*ODR_XL time.
Table 182. WAKE_UP_THS register
SINGLE_
DOUBLE
_TAP
INACTIVITY WK_THS5 WK_THS4 WK_THS3 WK_THS2 WK_THS1 WK_THS0