Datasheet
Register description LSM6DS3
70/99 DocID026899 Rev 7
9.54 FIFO_STATUS3 (3Ch)
FIFO status control register (r). For a proper reading of the register, it is recommended to set the
BDU bit in CTRL3_C (12h) to 1.
Table 139. FIFO_STATUS3 register
Table 140. FIFO_STATUS3 register description
9.55 FIFO_STATUS4 (3Dh)
FIFO status control register (r). For a proper reading of the register, it is recommended to set the
BDU bit in CTRL3_C (12h) to 1.
Table 141. FIFO_STATUS4 register
Table 142. FIFO_STATUS4 register description
9.56 FIFO_DATA_OUT_L (3Eh)
FIFO data output register (r). For a proper reading of the register, it is recommended to set the BDU bit
in CTRL3_C (12h) to 1.
FIFO_
PATTERN
_7
FIFO_
PATTERN
_6
FIFO_
PATTERN
_5
FIFO_
PATTERN
_4
FIFO_
PATTERN
_3
FIFO_
PATTERN
_2
FIFO_
PATTERN
_1
FIFO_
PATTERN
_0
FIFO_
PATTERN_[7:0]
Word of recursive pattern read at the next reading.
0
(1)
1. This bit must be set to ‘0’ for the correct operation of the device.
0
(1)
0
(1)
0
(1)
0
(1)
0
(1)
FIFO_
PATTERN_9
FIFO_
PATTERN_8
FIFO_
PATTERN_[9:8]
Word of recursive pattern read at the next reading.
Table 143. FIFO_DATA_OUT_L register
DATA_
OUT_
FIFO_L_7
DATA_
OUT_
FIFO_L_6
DATA_
OUT_
FIFO_L_5
DATA_
OUT_
FIFO_L_4
DATA_
OUT_
FIFO_L_3
DATA_
OUT_
FIFO_L_2
DATA_
OUT_
FIFO_L_1
DATA_
OUT_
FIFO_L_0
Table 144. FIFO_DATA_OUT_L register description
DATA_OUT_FIFO_L_[7:0] FIFO data output (first byte)