Datasheet

54/99 DocID026899 Rev 7

9.14 CTRL3_C (12h)

Control register 3 (r/w).

Table 52. CTRL3_C register

BOOT BDU H_LACTIVE PP_OD SIM IF_INC BLE SW_RESET

Table 53. CTRL3_C register description

BOOT Reboot memory content. Default value: 0

(0: normal mode; 1: reboot memory content

(1)

)

1. Boot request is executed as soon as internal oscillator is turned on. It is possible to set bit while in power-

down mode, in this case it will be served at the next normal mode or sleep mode.

BDU Block Data Update. Default value: 0

(0: continuous update; 1: output registers not updated until MSB and LSB have

been read)

H_LACTIVE Interrupt activation level. Default value: 0

(0: interrupt output pads active high; 1: interrupt output pads active low)

PP_OD Push-pull/open-drain selection on INT1 and INT2 pads. Default value: 0

(0: push-pull mode; 1: open-drain mode)

SIM SPI Serial Interface Mode selection. Default value: 0

(0: 4-wire interface; 1: 3-wire interface).

IF_INC Register address automatically incremented during a multiple byte access with a

serial interface (I

C or SPI). Default value: 1

(0: disabled; 1: enabled)

BLE Big/Little Endian Data selection. Default value 0

(0: data LSB @ lower address; 1: data MSB @ lower address)

SW_RESET Software reset. Default value: 0

(0: normal mode; 1: reset device)

This bit is cleared by hardware after next flash boot.