Datasheet

Digital interfaces LSM6DS3
32/99 DocID026899 Rev 7
6 Digital interfaces
The registers embedded inside the LSM6DS3 may be accessed through both the I
2
C and
SPI serial interfaces. The latter may be SW configured to operate either in 3-wire or 4-wire
interface mode.
The serial interfaces are mapped onto the same pins. To select/exploit the I
2
C interface, the
CS line must be tied high (i.e connected to Vdd_IO).
6.1 I
2
C serial interface
The LSM6DS3 I
2
C is a bus slave. The I
2
C is employed to write the data to the registers,
whose content can also be read back.
The relevant I
2
C terminology is provided in the table below.
There are two signals associated with the I
2
C bus: the serial clock line (SCL) and the Serial
DAta line (SDA). The latter is a bidirectional line used for sending and receiving the data
to/from the interface. Both the lines must be connected to Vdd_IO through external pull-up
resistors. When the bus is free, both the lines are high.
The I
2
C interface is implemeted with fast mode (400 kHz) I
2
C standards as well as with the
standard mode.
In order to disable the I
2
C block, (I2C_disable) = 1 must be written in CTRL4_C (13h).
Table 9. Serial interface pin description
Pin name Pin description
CS
SPI enable
I
2
C/SPI mode selection (1: SPI idle mode / I
2
C communication enabled;
0: SPI communication mode / I
2
C disabled)
SCL/SPC
I
2
C Serial Clock (SCL)
SPI Serial Port Clock (SPC)
SDA/SDI/SDO
I
2
C Serial Data (SDA)
SPI Serial Data Input (SDI)
3-wire Interface Serial Data Output (SDO)
SDO/SA0
SPI Serial Data Output (SDO)
I
2
C less significant bit of the device address
Table 10. I
2
C terminology
Term Description
Transmitter The device which sends data to the bus
Receiver The device which receives data from the bus
Master
The device which initiates a transfer, generates clock signals and terminates a
transfer
Slave The device addressed by the master