Datasheet
Rev. 1.10 26 May 16, 2011 Rev. 1.10 27 May 16, 2011
HT16K33
RAM Mapping 16*8 LED Controller Driver with keyscan
Acknowledge
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Each bytes includes eight bits is followed by a single acknowledge bit. This acknowledge bit is a
low level put on the bus by the receiver, the master generates an extra acknowledge related clock
pulse.
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A slave receiver which is addressed must generate an acknowledge (ACK) after the reception of
each byte.
●
The device that acknowledge must pull down the SDA line during the acknowledge clock pulse
so that it remains stable low during the high period of this clock pulse.
●
A master receiver must signal an end of data to the slave by generating a not-acknowledge (NACK)
bit on the last byte that has been clocked out of the slave. In this case, the master receiver must
leave the data line high during the 9th pulse to not acknowledge. The master will generate a STOP
or repeated START condition.
S
1 2
7 8
9
clk pulse for
acknowledgement
DATA OUTPUT
BY TRANSMITER
DATA OUTPUT
BY RECEIVER
SCL FROM
MASTER
acknowledge
not acknowledge
START
condition
Slave Addressing
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The HT16K33 device requires an 8-bit slave address word following a start condition to enable
the device for a write operation. The device address words consist of a mandatory one, zero
sequence for the rst four most signicant bits (refer to the diagram showing the slave Address).
This is common to all LED devices.
●
The slave address input circuit is shown below. A2~A0 are set to “0”, when A2~A0 are oating.
A2~A0 are to “1”, when A2~A0 are connected to an AD pin with a diode and resister.
●
The slave address set is loaded into the HT16K33 at every frame.
ROW2/A0
ROW1/A1
ROW0/A2
A0
A1
A2
HT16K33
COM0/AD
39KΩ*3
●
The slave address byte is the rst byte received following the START condition from the master
device. The first seven bits of the first byte make up the slave address. The eighth bit defines
whether a read or write operation is to be performed. When the R/W bit are “1”, then a read
operation is selected. A “0” selects a write operation.