Datasheet
Rev. 1.10 24 May 16, 2011 Rev. 1.10 25 May 16, 2011
HT16K33
RAM Mapping 16*8 LED Controller Driver with keyscan
I
2
C Serial Interface
The HT16K33 includes an I
2
C serial interface. The I
2
C bus is used for bidirectional, two-line com-com-
munication between different ICs or modules. The two lines are a serial data line (SDA) and a serial
clock line (SCL). Both lines are connected to a positive supply via a pull-up resistor. When the bus
is free, both lines are high. The output stages of devices connected to the bus must have an open-
drain or open-collector to perform a wired and function. Data transfer is initiated only when the bus
is not busy.
Data validity
The data on the SDA line must be stable during the high period of the clock. The high or low state of
the data line can only change when the clock signal on the SCL line is Low (see below).
SDA
SCL
Data line stable,
Data valid
Chang of data
allowed
START and STOP conditions
●
A high to low transition on the SDA line while SCL is high denes a START condition.
●
A low to high transition on the SDA line while SCL is high denes a STOP condition.
●
START and STOP conditions are always generated by the master. The bus is considered to be
busy after the START condition. The bus is considered to be free again a certain time after the
STOP condition.
●
The bus stays busy if a repeated START (Sr) is generated instead of a STOP condition. In this
respect, the START(S) and repeated START (Sr) conditions are functionally identical.
PS
SDA
SCL
SDA
SCL
START condition STOP condition
Byte format
Every byte put on the SDA line must be 8-bits long. The number of bytes that can be transmitted per
transfer is unrestricted. Each byte has to be followed by an acknowledge bit. Data is transferred with
the most signicant bit (MSB) rst.
S
or
Sr
P
or
Sr
SDA
SCL
1 2 7 8
9
ACK
1 2 3-8
9
ACK
P
Sr