Datasheet
Rev. 1.10 6 May 16, 2011 Rev. 1.10 7 May 16, 2011
HT16K33
RAM Mapping 16*8 LED Controller Driver with keyscan
A.C. Characteristics
Symbol Parameter
Test condition
Min. Max. Unit
condition
f
SCL
Clock frequency — — 400 kHZ
t
BUF
Bus free time
Time in which the bus must be free before a new
transmission can start
1.3 — μs
t
HD; STA
Start condition hold time
After this period, the rst clock pulse is generated
0.6 — μs
t
LOW
SCL Low time — 1.3 — μs
t
HIGH
SCL High time — 0.6 — μs
t
SU; STA
Start condition set-up time Only relevant for repeated START condition. 0.6 — μs
t
HD; DAT
Data hold time — 0 — μs
t
SU; DAT
Data set-up time — 100 — ns
t
r
Rise time Note — 0.3 μs
t
f
Fall time Note — 0.3 μs
t
SU; STO
Stop condition set-up time — 0.6 — μs
t
AA
Output Valid from Clock — — 0.9 μs
t
SP
Input Filter Time Constant
(SDA and SCL Pins)
Noise suppression time — 50 ns
Note: These parameters are periodically sampled but not 100% tested.
Timing Diagrams
● I
2
C Timing
SDA
SCL
t
f
t
HD:SDA
t
LOW
t
r
t
HD:DAT
t
SU:DAT
t
HIGH
t
SU:STA
t
HD:STA
S
Sr
t
SP
t
SU:STO
P
t
BUF
S
t
AA
SDA
OUT
● Power-on Reset Timing