Datasheet

1
Sipeed Tang Nano Datasheet v1.0
Sipeed Technology
UPDATE
V1.0
Edited October 9, 2019; original document
SPECIFICATION
FPGA chip
GW1N-1-LV：
• LUT4 : 1152
• Flip-Flop(FF) : 864
• Block SRAM (bits) : 72K
• B-SRAM quantity : 4
• User Flash(bits) : 96K
• PLLs+DLLs : 1+0
• Total number of I/O banks : 4
• Core Voltage (LV) : 1.2V
Download method
Simply plug in the USB cable and download it via the onboard
downloader
Power circuit
Each BANK occupies a separate LDO power chip (except
BANK0/3)
Adjust the IO level of BANK1 and BANK2 by replacing the LDO
chip by yourself.
40P FPC LCD carrier
Standard 40P RGB LCD interface
On-board screen backlight driver circuit (default normally
open, EN pin can be connected to FPGA)
IO
34 IO ports and multiple power pins on both sides
Both sides of the pins can be directly inserted into the
breadboard
Onboard PSRAM chip
Capacity: 64Mbit
Voltage: 3.3V
Power supply and download interface
USB-typeC interface
RGB LED
Onboard small size RGB LED
button
2 3x4mm buttons onboard
Crystal oscillator
Onboard 24Mhz crystal oscillator (started by CH552)
Software information
IDE
IDE http://www.gowinsemi.com.cn/faq.aspx
License
Floating lic or stand-alone version lic, see for details http:/
/dl.sipeed.com/TANG/Nano/IDE