Datasheet
Note: If booting the SoM in eFUSE mode (default behavior), all SAI pins are available during boot.
However, when using the other boot modes, pins SAI1_RX[7:0] and SAI1_TX[7:0] are used to enable boot
configuration overrides by latching them to the BOOT_CFG[15:0] bits in the SoC—that is, only until boot
completes. The SoM uses internal pin strap (pull-up and pull-down) resistors to select the different boot
configuration, so you should be careful if you add any pull-up/down resistors for these pins on your
baseboard. For details, see the IMX8M SoC documentation.
Version 1.2 (August 2019)
Table 17. SAI 1 signals
Name Type Connector Pins Voltage Description
SAI1_MCLK I/O J1312 26 3.3V Audio master clock
SAI1_RXC Input J1312 17 3.3V Receive bit clock
SAI1_RXFS Input J1312 19 3.3V Receive frame sync
SAI1_RXD0 Input J1312 33 3.3V Receive channel.
Reserved during boot, except in eFUSE mode. See note
above.
SAI1_RXD1 Input J1312 35 3.3V Receive channel.
Pull-up in SoM: 10k Ohm.
Reserved during boot, except in eFUSE mode. See note
above.
SAI1_RXD2 Input J1312 27 3.3V Receive channel.
Reserved during boot, except in eFUSE mode. See note
above.
SAI1_RXD3 Input J1312 31 3.3V Receive channel.
Pull-down in SoM: 10k Ohm.
Reserved during boot, except in eFUSE mode. See note
above.
SAI1_RXD4 Input J1312 29 3.3V Receive channel.
Pull-down in SoM: 10k Ohm.
Reserved during boot, except in eFUSE mode. See note
above.
SAI1_RXD5 Input J1312 21 3.3V Receive channel.
Pull-up in SoM: 10k Ohm.
Reserved during boot, except in eFUSE mode. See note
above.
SAI1_RXD6 Input J1312 25 3.3V Receive channel.
Pull-down in SoM: 10k Ohm.
Reserved during boot, except in eFUSE mode. See note
above.
Copyright 2019 Google LLC. All rights reserved.