Datasheet

Ethernet
The Ethernet Media Access Controller (MAC) supports 10/100/1000 Mbps Ethernet/IEEE 802.3 networks with reduced
gigabit media-independent interface (RGMII). Requires an Ethernet PHY on the baseboard.
Version 1.2 (August 2019)
Table 14. Ethernet pins
Name Type Connector Pins Voltage Description
ENET_RD0 Input J1310 33 1.8V RGMII receive from PHY
ENET_RD1 Input J1310 35 1.8V RGMII receive from PHY
ENET_RD2 Input J1310 31 1.8V RGMII receive from PHY
ENET_RD3 Input J1310 37 1.8V RGMII receive from PHY
ENET_RX_CTL Input J1310 29 1.8V RGMII receive from PHY
ENET_RXC Input J1310 27 1.8V RGMII receive from PHY
ENET_TD0 Output J1310 19 1.8V RGMII transmit to PHY
ENET_TD1 Output J1310 21 1.8V RGMII transmit to PHY
ENET_TD2 Output J1310 17 1.8V RGMII transmit to PHY
ENET_TD3 Output J1310 15 1.8V RGMII transmit to PHY
ENET_TX_CTL Output J1310 13 1.8V RGMII transmit to PHY
ENET_TXC Output J1310 23 1.8V RGMII transmit to PHY
ENET_MDC Output J1310 11 1.8V RGMII clock for PHY
ENET_MDIO Output J1310 9 1.8V RGMII MDIO data for PHY
ENET_nRST
(GPIO1_IO09)
Output J1312 43 3.3V PHY reset
ENET_nINT
(GPIO1_IO11)
Input J1312 39 3.3V PHY interrupt
ENET_WoL
(GPIO1_IO10)
Input J1312 41 3.3V PHY Wake-on-Lan
CLKO_25M
(GPIO1_IO15)
Output J1310 54 3.3V Optional 25Mhz clock to PHY
Copyright 2019 Google LLC. All rights reserved.