System-On-Module Datasheet Version 1.2 Version 1.2 (August 2019) Copyright 2019 Google LLC. All rights reserved.
Features NXP i.MX 8M SoC Quad-core ARM Cortex-A53, plus Cortex-M4F 2D/3D Vivante GC7000 Lite GPU and VPU Google Edge TPU ML accelerator Cryptographic coprocessor Wi-Fi 2x2 MIMO (802.11b/g/n/ac 2.4/5GHz) Bluetooth 4.2 8GB eMMC 1GB LPDDR4 USB 3.
Table of contents System components Block diagrams Mechanical dimensions Environmental reliability Certifications System power Power signals Power consumption Boot mode Peripheral interfaces MIPI camera (CSI) MIPI display (DSI) HDMI Ethernet PCIe USB Digital audio (SAI) Sony/Philips audio (SPDIF) Micro-SD card JTAG debugging I2C UART SPI GPIO PWM Wi-Fi and Bluetooth Baseboard developer guide Reference design Baseboard connectors Connectors, keepouts, and component max heights Trace impedance recommendations
System components Table 1. Available SoM components and features Feature Details Main system-on-chip (i.MX8M) Arm Cortex-A53 MPCore platform Quad symmetric Cortex-A53 processors: 32 KB L1 Instruction Cache 32 KB L1 Data Cache Support L1 cache RAMs protection with parity/ECC Support of 64-bit Armv8-A architecture: 1 MB unified L2 cache Support L2 cache RAMs protection with ECC Frequency of 1.
Feature I/O connectivity Details 2x USB 3.0/2.
Feature Details Display HDMI Display Interface: HDMI 2.
Feature Edge TPU coprocessor Details ASIC designed by Google that provides high performance ML inferencing for TensorFlow Lite models Uses PCIe and I2C/GPIO to interface with the iMX8M SoC 4 trillion operations per second (TOPS) 2 TOPS per watt Memory and storage Random access memory (SDRAM) 1GB LPDDR4 SDRAM (4-channel, 32-bit bus width) 1600MHz maximum DDR clock Interfaces directly to the iMX8M build-in DDR controller Flash memory (eMMC) 8GB NAND eMMC flash memory 8-bits MMC mode Conforms to JEDEC ver
Feature Details Hardware interface Baseboard connectors 3x 100-pin connectors (Hirose DF40C-100DP-0.4V) Antenna connectors 2x coaxial cable connectors (Murata MM8930-2600) Block diagrams Figures 1 and 2 illustrate the core components on the SoM and SoC. Figure 1. Block diagram of the SoM components Version 1.2 (August 2019) Copyright 2019 Google LLC. All rights reserved.
Figure 2. Block diagram of the i.MX8M SoC components, provided by NXP (some I/O signals on the SoC are consumed on the SoM, so refer to table 1 for availability) Version 1.2 (August 2019) Copyright 2019 Google LLC. All rights reserved.
Mechanical dimensions Table 2. SoM mechanical dimensions Measurement Value Size 48 x 40 x 5.11 mm Weight 13 g Figure 3 illustrates all of the SoM's dimensions. For a top-down view of the baseboard connector locations and component height restrictions, see the Baseboard developer guide. Figure 3. SoM dimensions (in millimeters) Version 1.2 (August 2019) Copyright 2019 Google LLC. All rights reserved.
Environmental reliability Table 3. SoM environmental and mechanical limits Measurement Limits Shock 50G/20ms Vibration 20G/0-600Hz MTTF >200,000 hours Operation temperature 0 to 50°C Storage temperature -40 to 85°C Relative humidity 10% to 90% (operation) 5% to 95% (storage) Certi cations Table 4. SoM certifications Market Certifications USA FCC European Union CE System power The SoM requires 5V as power input (at VSYS_5V).
Caution: Do not connect the 1.8V/3.3V power output pins to any high current devices or you might brownout the system. These power lines are shared with internal SoM circuits, so there is no safe limit for a high current device, but you can safely use them for low current tasks such as for a level shifter or pullup/down. Caution: Do not connect any of the 3.3V I/O pins to a device that draws more than ~ 82 mA of power or you will brownout the system.
Name Type Connector Pins Voltage Description VDD_3V3 Power J1310 94, 96, 98 100 3.3V 3.3V output from SoM. Can be left floating if not used. Not for high-current usage; can be used to pullup GPIO. VDDA_1V8 Power J1310 91, 93, 95, 97, 99 1.8V 1.8V output from SoM. Can be left floating if not used. Not for high-current usage; can be used to pullup GPIO. POR_B Output J1310 79 3.
Figure 4.
Boot mode Use the BOOT_MODE[1:0] pins to configure the SoM boot mode setting as indicated in the following tables. Table 8. Boot mode pin signals Name Type Connector Pins Voltage Description BOOT_MODE0 Input J1312 64 3.3V SoC BOOT_MODE0 signal (can be set by switch or pinstrap on baseboard) BOOT_MODE1 Input J1312 62 3.3V SoC BOOT_MODE1 signal (can be set by switch or pinstrap on baseboard) Table 9.
Peripheral interfaces The following interfaces are available from the SoM, through the three 100-pin board-to-board connectors. This section is organized based on the default pin functions when running the Mendel operating system. For information about alternative pin functions you may enable with your own device tree overlay, see the iMX8M SoC documentation.
Table 11. CSI channel 2 pins Name Type Connector Pins Voltage Description MIPI_CSI2_CLK_P/N Input J1311 36/34 0.2-1.2V MIPI CSI2 clock (positive/negative) MIPI_CSI2_D0_P/N Input J1311 35/33 0.2-1.2V MIPI CSI2 data (positive/negative) MIPI_CSI2_D1_P/N Input J1311 30/28 0.2-1.2V MIPI CSI2 data (positive/negative) MIPI_CSI2_D2_P/N Input J1311 24/22 0.2-1.2V MIPI CSI2 data (positive/negative) MIPI_CSI2_D3_P/N Input J1311 41/39 0.2-1.
HDMI The High-Definition Multimedia Interface (HDMI) connection provides the following features: HDMI 2.0a supporting one display up to 1080p Upscale and downscale between 4K and HD video (requires full system resources) 20+ Audio interfaces 32-bit @ 384 kHz fs, with Time Division Multiplexing (TDM) support SPDIF input and output Audio Return Channel (ARC) on HDMI Table 13. HDMI pins Name Type Connector Pins Voltage Description HDMI_REFCLKP/N Output J1310 58/60 3.
Ethernet The Ethernet Media Access Controller (MAC) supports 10/100/1000 Mbps Ethernet/IEEE 802.3 networks with reduced gigabit media-independent interface (RGMII). Requires an Ethernet PHY on the baseboard. Table 14. Ethernet pins Name Type Connector Pins Voltage Description ENET_RD0 Input J1310 33 1.8V RGMII receive from PHY ENET_RD1 Input J1310 35 1.8V RGMII receive from PHY ENET_RD2 Input J1310 31 1.8V RGMII receive from PHY ENET_RD3 Input J1310 37 1.
PCIe The SoC includes PCIE1 and PCIE2 lines that are routed to the baseboard connectors, but you should not need to connect these and you should not remap these with your own device tree because both are used on the SoM for Wi-Fi (PCIE1) and the Edge TPU (PCIE2). USB There are two USB controllers and corresponding PHYs on the SoM. Each USB instance contains USB 3.0 core, which can operate in both USB 3.0 and 2.0 mode. Table 15.
Note: If booting the SoM in eFUSE mode (default behavior), all SAI pins are available during boot. However, when using the other boot modes, pins SAI1_RX[7:0] and SAI1_TX[7:0] are used to enable boot configuration overrides by latching them to the BOOT_CFG[15:0] bits in the SoC—that is, only until boot completes.
Name Type Connector Pins Voltage Description SAI1_RXD7 Input J1312 23 3.3V Receive channel. Pull-down in SoM: 10k Ohm. Reserved during boot, except in eFUSE mode. See note above. SAI1_TXC Output J1312 40 3.3V Transmit bit clock. SAI1_TXFS Output J1312 46 3.3V Transmit frame sync. SAI1_TXD0 Output J1312 44 3.3V Transmit channel. Pull-down in SoM: 10k Ohm. Reserved during boot, except in eFUSE mode. See note above. SAI1_TXD1 Output J1312 42 3.3V Transmit channel.
Table 18. SAI 2 signals Name Type Connector Pins Voltage Description SAI2_TXD Output J1312 14 3.3V Transmit channel SAI2_RXD Input J1312 20 3.3V Receive channel SAI2_TXC Output J1312 18 3.3V Transmit bit clock SAI2_TXFS Output J1312 16 3.3V Transmit frame sync SAI2_MCLK I/O J1312 12 3.3V Audio master clock SAI2_RXFS Input J1312 24 3.3V Receive frame sync SAI2_RXC Input J1312 23 3.
Micro-SD card An Ultra Secure Digital Host Controller (uSDHC) module provides the interface between the host and SD/SDIO/MMC cards, with the following features: SD/SDIO standard, up to version 3.0 MMC standard, up to version 5.0 3.3V operation only 1- and 4-bit SD/SDIO/MMC modes Table 20. SD/MMC pin signals Name Type Connector Pins Voltage Description SD2_CLK Output J1310 48 3.3V Serial clock SD2_CMD Output J1310 26 3.
JTAG debugging 5-pin JTAG debugging with a Secure JTAG Controller (SJC) for secure debugging. Table 21. JTAG pin signals Name Type Connector Pins Voltage Description JTAG_TMS Output J1312 59 3.3V Test mode select JTAG_TDI Input J1312 61 3.3V Test data in JTAG_TDO Output J1312 57 3.3V Test data out JTAG_TCK Output J1312 53 3.3V Test clock JTAG_nTRST Input J1312 55 3.3V Test reset I2C Two I2C bus interfaces are available. Table 22.
UART Two UART v2 modules are available with the following features: 7- or 8-bit data words, 1 or 2 stop bits, programmable parity (even, odd, or none). Programmable baud rates up to 4 Mbps. 32-byte FIFO on Tx and 32 half-word FIFO on Rx supporting auto-baud. Note: By default, the Mendel operating system configures UART1 for use with the the serial console. Table 23. UART pin signals Name Type Connector Pins Voltage Description UART1_TXD Output J1311 93 3.
Table 25. SPI channel 2 pin signals Name Type Connector Pins Voltage Description ECSPI2_MISO Input J1312 3 3.3V Master input ECSPI2_MOSI Output J1312 6 3.3V Master output ECSPI2_SCLK Output J1312 2 3.3V Serial clock ECSPI2_SS0 Output J1312 1 3.3V Chip select ECSPI2_SS1 Output J1310 4 3.3V Chip select GPIO The following pins are configured for general purpose input/output, by default.
Name Type Connector Pins Voltage Description SAI5_RXD0 I/O J1312 58 3.3V GPIO SAI5_RXD2 I/O J1312 54 3.3V GPIO PWM There are four PWM output pins available with 16-bit resolution and 4x16 data FIFO. Table 27. PWM pin signals Name Type Connector Pins Voltage Description PWM1 (GPIO1_IO01) Output J1312 88 3.3V PWM or GPIO PWM2 (GPIO1_IO013) Output J1312 90 3.3V PWM or GPIO PWM3 (GPIO1_IO014) Output J1312 92 3.3V PWM or GPIO PWM4 (SAI3_MCLK) Output J1312 11 3.
Baseboard developer guide This section provides details to help you integrate the Coral SoM into your own baseboard (carrier board) hardware. Reference design If you'd like to see a reference baseboard design, download the following schematic and layout files for the Coral Dev Board. File Description Coral-Dev-Board-baseboard-schematic.pdf Baseboard schematic in PDF Coral-Dev-Board-baseboard-schematic-Altium.zip Baseboard schematic files in Altium format Coral-Dev-Board-baseboard-layout-Allegro.
Connectors, keepouts, and component max heights Figure 5 illustrates the area of your baseboard where the SoM connects. The measurements are relative to the standoff in the bottom-left corner, indicating the position for the three board-to-board (B2B) connectors (Hirose DF40C-100DP0.4V), two standoffs, and the following component regions: A. Antenna keepout: Place no components and no copper in this region.
Trace impedance recommendations The following table lists the recommended impedance for high-speed signals on the baseboard. Table 29.
Table 31. CSI channel 2 signal trace length on SoM Name Etch length (mils) Manhattan length (mils) MIPI_CSI2_CLKN 299.51 282.39 MIPI_CSI2_CLKP 301.92 323.73 MIPI_CSI2_D0N 258.48 252.46 MIPI_CSI2_D0P 258.58 293.81 MIPI_CSI2_D1N 289.71 260.74 MIPI_CSI2_D1P 292.95 302.08 MIPI_CSI2_D2N 293.48 266.24 MIPI_CSI2_D2P 298.18 280.42 MIPI_CSI2_D3N 265.86 274.12 MIPI_CSI2_D3P 268.14 315.46 Table 32.
Other recommendations Make sure to route all the VSYS_5V and GND pins, and add decoupling (bypass) capacitors between VSYS_5V and GND near the mating connector pins. When placing a pull-up or pull-down resistor on some of the SoM signals, such as I/O pins (especially SAI1_TXD[7:0] and SAI1_RXD[7:0]), review the signal description for each peripheral interface, because some of them already have pull-up/down resistor in the SoM for initialization purposes.
Figure 6. SoM connector schematic (click to enlarge) Version 1.2 (August 2019) Copyright 2019 Google LLC. All rights reserved.
Document revisions Table 33. History of changes to this document Version Changes 1.2 (August 2019) Add PDF download of this datasheet and the Dev Board baseboard schematic. 1.1 (July 2019) Remove wireless antenna connector details. 1.0 (June 2019) Initial release Version 1.2 (August 2019) Copyright 2019 Google LLC. All rights reserved.
